A
alivingstone
I'm trying to populate a sparse SLV using aggregate notation, but it's
apparently not legal VHDL. Anyone have any ideas on how I could
implement the following snippet...
constant M1 : integer := 7; --marker1
constant M2 : integer := 80;
subtype DATA is std_logic_vector(31 downto 0);
constant D1 : DATA := x"00112233"; --data1
constant D2 : DATA := x"44556677";
subtype FRAME is std_logic_vector(0 to 1023);
constant F : FRAME := (
M1 to M1 + DATA'length => D1,
M2 to M2 + DATA'length => D2,
others => '0'
);
My intent is to populate only select portions of the large
std_logic_vector F and set the rest to '0'.
Much appreciated.
apparently not legal VHDL. Anyone have any ideas on how I could
implement the following snippet...
constant M1 : integer := 7; --marker1
constant M2 : integer := 80;
subtype DATA is std_logic_vector(31 downto 0);
constant D1 : DATA := x"00112233"; --data1
constant D2 : DATA := x"44556677";
subtype FRAME is std_logic_vector(0 to 1023);
constant F : FRAME := (
M1 to M1 + DATA'length => D1,
M2 to M2 + DATA'length => D2,
others => '0'
);
My intent is to populate only select portions of the large
std_logic_vector F and set the rest to '0'.
Much appreciated.