problem: unwanted latches inferred

[kelvinyung]

Hello everyone!

I am new to VHDL. I ran into a problem of "unwanted latches". ("Latches may be generated from incomplete case or if statements."). I searched on the internet about this warning but it seems I could not find an answer that specially applies to my case.

Here are some details:
The code is a finite statement machine. When I synthesize the VHDL code, it gave me some warnings about generating latches for a few signals. I did use CASE statement.
But I think I already assigned value to every signal/variable in each case. I checked my code multiple times but still have no clue why it always gave me such a warning message.

The problemetic signals/variables in my code are "sel1_val0", "sel1_val1", "sel2_val", "sec_counter", "plane_counter".

Could some help me by taking a look into my code? I have my code in the attachment. It is too long to paste it within this thread. Thanks a lot in advance.

 

[joris]

The problem is that you do:

sel1_val0 := sel1_val0;
sel1_val1 := sel1_val1;
sel2_val := sel2_val;
sec_counter := sec_counter;
plane_counter := plane_counter;

Those depend on the previous values of the variables (obviously), which causes latches to be inferred.

One way to avoid this problem is by merging the two processes into a single process.

To keep the two processes design, would be using signals like next_sel1_var0 (and replacing the current variables with signals), etc, which would then get set together with the state variable.
Making the code I quoted above, like this:

next_sel1_val0 <= sel1_val0;
next_sel1_val1 <= sel1_val1;
next_sel2_val <= sel2_val;
next_sec_counter <= sec_counter;
next_plane_counter <= plane_counter;

 

[kelvinyung]

Thanks for the solution! That's exactly the problem. I solved it with your suggestion. Thank you!:grin: