problem whit program ycrcb to rgb

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this is ycrcb
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ycrcb_to_rgb is
port (
icb:in std_logic_vector(7 downto 0);
icr:in std_logic_vector(7 downto 0);
iy:in std_logic_vector(7 downto 0);
x : out std_logic_vector (26 downto 0);
z : out std_logic_vector (26 downto 0);
y : out std_logic_vector (26 downto 0);

aval:in std_logic_vector (16 downto 0);
bval:in std_logic_vector (16 downto 0);
cval:in std_logic_vector (16 downto 0);
dval:in std_logic_vector (16 downto 0);
fval:in std_logic_vector (16 downto 0);
red : out std_logic_vector (9 downto 0);
green: out std_logic_vector (9 downto 0);
blue: out std_logic_vector (9 downto 0);
iCLK : in std_logic;
ireset : in std_logic);

end ycrcb_to_rgb;

architecture behave of ycrcb_to_rgb is

component mac3
port (
aclr0 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
dataa_2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (16 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (16 DOWNTO 0) := (OTHERS => '0');
datab_2 : IN STD_LOGIC_VECTOR (16 DOWNTO 0) := (OTHERS => '0');
result : OUT STD_LOGIC_VECTOR (26 DOWNTO 0));
end component;
signal x_i,y_i,z_i:integer range 0 to 134217727;
signal x_v,y_v,z_v:std_logic_vector(26 downto 0);
signal x_vs,y_vs,z_vs:std_logic_vector(6 downto 0);
signal x_out,y_out,z_out:std_logic_vector(28 downto 0);
signal ored,ogreen,oblue:std_logic_vector(9 downto 0);
begin


m1 : mac3
port map (
dataa_0=>iy;
dataa_1=>icb;
dataa_2=>icr;

datab_0=>aval;
datab_1=>bval;
datab_2=>cval;

clock0 => iCLK;
aclr0 => ireset;
aval<="00000001001010100";
bval<="00000000000000000";
cval<="00000001100110001");

m2 : mac3
port map(
dataa_0=>iy;
dataa_1=>icb;
dataa_2=>icr;

datab_0=>aval;
datab_1=>dval;
datab_2=>eval;

clock0 => iCLK;
aclr0 => ireset;
aval<="00000001001010100";
dval<="11111111100111000";
eval<="11111111001100000");
m3 : mac3
port map
(
dataa_0=>iy;
dataa_1=>icb;
dataa_2=>icr;

datab_0=>aval;
datab_1=>fval;
datab_2=>bval;

clock0 => iCLK;
aclr0 => ireset;
fval<="00000010000001001";
aval<="00000001001010100";
bval<="00000000000000000");
------------------------------------
x_i<=conv_integer(x)-144131;
y_i<=conv_integer(y)+69370;
z_i<=conv_integer(z)-141787;
------------------------------------
x_v<= x_i +"000000000000000000000000000";
y_v<= y_i +"000000000000000000000000000";
z_v<= z_i +"000000000000000000000000000";
----------------------------------------
x_vs <= "0000000" & x_v (26 downto 7);
y_vs <= "0000000" & y_v (26 downto 7);
z_vs <= "0000000" & z_v (26 downto 7);
-----------------------------------------------------------------------
-----------------------------------------------------------------------
process(ireset,iclk)
begin
if ireset='1' then
x_out<=(others=>'0');
y_out<=(others=>'0');
z_out<=(others=>'0');
elsif (iclk'event and clock='1') then
x_out<=x_vs(19 downto 0);
y_out<=y_vs(19 downto 0);
z_out<=z_vs(19 downto 0);
end if;
x<=x_out;
z<=z_out;
y<=y_out;
end process;

process (ireset,iclk)
begin
if ireset='1' then
ored <= (others=>'0');
ogreen <= (others=>'0');
oblue <= (others=>'0');
elsif (iclk'event and clock='1') then if
x_out(19)='1' then
ored <=(others=>'0');
elsif
x_out(18 downto 0)>1023 then
ored <="1111111111";
else
ored <= x_out(9 downto 0);
end if;

if
y_out(19)='1' then
ogreen <=(others=>'0');
elsif x_out(18 downto 0)>1023 then
ogreen <="1111111111";
else
ogreen <= y_out(9 downto 0);
end if;

if
x_out(19)='1' then
oblue <=(others=>'0');
elsif z_out(18 downto 0)>1023 then
oblue <="1111111111";
else
oblue <= z_out(9 downto 0);
end if;
end if;
end process;
red <=ored;
green<= ogreen;
blue <= oblue;
end behave;


the problem is:
Error (10500): VHDL syntax error at ycrcb_to_rgb.vhd(51) near text ";"; expecting ")", or ","
Error (10500): VHDL syntax error at ycrcb_to_rgb.vhd(67) near text ";"; expecting ")", or ","
Error (10500): VHDL syntax error at ycrcb_to_rgb.vhd(83) near text ";"; expecting ")", or ","
Info: Found 0 design units, including 0 entities, in source file ycrcb_to_rgb.vhd
Info: Found 2 design units, including 1 entities, in source file mac3.vhd
Info: Found design unit 1: mac3-SYN
Info: Found entity 1: mac3
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
Error: Peak virtual memory: 191 megabytes
Error: Processing ended: Thu Sep 16 09:54:38 2010
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 5 errors, 0 warnings
 
Last edited:

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