Problem with assignment Schedule in Modelsim?

Discussion in 'VHDL' started by Tricky, Aug 10, 2007.

  1. Tricky

    Tricky Guest

    Ive used the following code in my testbench.
    KILLSIM is a boolean used as a timeout incase the testbench isnt
    working (and therefore wont run foreever). This should always be set
    so that it can only go true after all input and output has completed
    (effectively ending the testbench)

    ENDSIM is set when all input and output has finished (from whatever
    stimulus).

    ------------------------------------------------------------------------------------------------
    --clk_proc : process to generate the clock
    ------------------------------------------------------------------------------------------------
    clk_proc : process
    begin

    KILLSIM <= false, true after TIMEOUT*CLK_PERIOD;

    while not ENDSIM loop
    if clk /= '0' then
    clk <= '0';
    else
    clk <= '1';
    end if;

    wait for CLK_PERIOD/2;
    end loop;

    --remove KILLSIM assignment schedule
    KILLSIM <= KILLSIM;

    --give 1 more clock cycle
    clk <= not clk;
    wait for CLK_PERIOD/2;
    clk <= not clk;

    if KILLSIM then
    report "Simulation ended after KILLSIM timeout" severity warning;
    end if;

    wait;
    end process;

    reset <= '1', '0' after RESET_PERIOD*CLK_PERIOD;

    ENDSIM <= (endsim_ip and endsim_op) or KILLSIM;


    When running a testbench in modelsim using this code, ENDSIM occurs
    correctly after all stimulus and expected results are finished, but
    the simulation still runs until timout. If I remove the line:
    KILLSIM <= false, true after TIMEOUT*CLK_PERIOD;

    then the simulation ends as expected.

    Im sure Ive used this code in ActiveHDL before and IIRC it ran
    correctly. Is there any reason why KILLSIM <= KILLSIM is not removing
    the previous assignment scheduled?
    The same thing happens if I assign
    KILLSIM <= false;

    if not KILLSIM then KILLSIM <= false; end if;
    Tricky, Aug 10, 2007
    #1
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  2. In news:
    timestamped Fri, 10 Aug 2007 08:24:44 -0700,
    Tricky <> posted:
    |-------------------------------------------------------------------------------|
    |"[..] |
    | |
    |-------------------------------------------------------------------------------|
    |----------------- |
    | --clk_proc : process to generate the clock |
    | -----------------------------------------------------------------------|
    |------------------------- |
    | clk_proc : process |
    | begin |
    | |
    | KILLSIM <= false, true after TIMEOUT*CLK_PERIOD; |
    | |
    | while not ENDSIM loop |
    | if clk /= '0' then |
    | clk <= '0'; |
    | else |
    | clk <= '1'; |
    | end if; |
    | |
    | wait for CLK_PERIOD/2; |
    | end loop; |
    | |
    | --remove KILLSIM assignment schedule |
    | KILLSIM <= KILLSIM; |
    | |
    | --give 1 more clock cycle |
    | clk <= not clk; |
    | wait for CLK_PERIOD/2; |
    | clk <= not clk; |
    | |
    | if KILLSIM then |
    | report "Simulation ended after KILLSIM timeout" severity warn|
    |ing; |
    | end if; |
    | |
    | wait; |
    | end process; |
    | |
    | reset <= '1', '0' after RESET_PERIOD*CLK_PERIOD; |
    | |
    | ENDSIM <= (endsim_ip and endsim_op) or KILLSIM; |
    | |
    | |
    |When running a testbench in modelsim using this code, ENDSIM occurs |
    |correctly after all stimulus and expected results are finished, but |
    |the simulation still runs until timout. If I remove the line: |
    | KILLSIM <= false, true after TIMEOUT*CLK_PERIOD; |
    | |
    |then the simulation ends as expected. |
    | |
    |Im sure Ive used this code in ActiveHDL before and IIRC it ran |
    |correctly. Is there any reason why KILLSIM <= KILLSIM is not removing |
    |the previous assignment scheduled?" |
    |-------------------------------------------------------------------------------|

    I could be mistaken, but I believe that KILLSIM <= KILLSIM; should
    have the effect you tried to achieve with it.

    |-------------------------------------------------------------------------------|
    |"The same thing" |
    |-------------------------------------------------------------------------------|

    The same thing as what?

    Regards,
    Colin Paul Gloster

    |-------------------------------------------------------------------------------|
    |" happens if I assign |
    |KILLSIM <= false; |
    | |
    |if not KILLSIM then KILLSIM <= false; end if;" |
    |-------------------------------------------------------------------------------|
    Colin Paul Gloster, Aug 11, 2007
    #2
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  3. Tricky

    Tricky Guest


    >
    > I could be mistaken, but I believe that KILLSIM <= KILLSIM; should
    > have the effect you tried to achieve with it.


    Thats what I thought, but Modelsim seems to be changing the assignment
    value (ie, its now always false) but not removing the schedule, so it
    just continues running until the given timeout. I guess I just found a
    quirk with this version of modelsim.

    >
    > |-------------------------------------------------------------------------------|
    > |"The same thing" |
    > |-------------------------------------------------------------------------------|
    >
    > The same thing as what?
    >


    Assigning it to false instead of itself did the same thing as I stated
    in the first place - the simulator didnt stop, but KILLSIM held the
    false value.
    Tricky, Aug 13, 2007
    #3
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