Problem with Behav Sim vs Post Place & Route Sim

Discussion in 'VHDL' started by joel.weddick@lmco.com, Sep 22, 2005.

  1. Guest

    I have a real simple piece of code where I am setting a signal in the
    test bench and generating an ack signal in the main code. I have coded
    it using state machines since I plan to add to it once I figure out why
    it won't work in Post Place & route. The code is shown below.

    Thanks in advance for any help..

    Joel

    -- MAIN CODE
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity CDEout is
    Port (
    FPGA_CLK : in std_logic;
    LRESET_n : in std_logic;
    LHOLD : in std_logic;
    LHOLDA : out std_logic
    );
    end CDEout;

    architecture RTL of CDEout is

    type State_Type is (S0,S1,S2);

    signal Current_State : State_Type;
    signal Next_State : State_Type;

    signal CLK : std_logic;
    signal RESET : std_logic;

    signal set_holda : boolean;
    signal rst_holda : boolean;


    begin

    CLK <= FPGA_CLK;
    RESET <= not LRESET_n;

    Sync: PROCESS( CLK, RESET)
    begin

    if (RESET = '1') then
    current_state <= S0;
    elsif (rising_edge(CLK)) then
    current_state <= next_state;
    end if;

    end process;


    PROCESS( CLK, RESET )
    begin
    if (RESET = '1') then
    LHOLDA <= '0';
    elsif (rising_edge(CLK)) then
    if (set_holda) then
    LHOLDA <= '1';
    elsif (rst_holda) then
    LHOLDA <= '0';
    end if;
    end if;
    end process;


    Comb: PROCESS(Current_State, LHOLD)
    begin

    set_holda <= FALSE;
    rst_holda <= FALSE;

    case Current_State is

    when S0 =>
    if (LHOLD = '1') then
    set_holda <= TRUE;
    next_state <= S1;
    else
    set_holda <= FALSE;
    next_state <= S0;
    end if;


    when S1 =>

    next_state <= S2;

    when S2 =>

    next_state <= S1;

    end case;
    end process;

    end RTL;


    -- TEST BENCH

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.all;
    USE ieee.numeric_std.ALL;

    ENTITY CDEout_tb_vhd IS
    END CDEout_tb_vhd;

    ARCHITECTURE behavior OF CDEout_tb_vhd IS

    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT cdeout
    PORT(
    FPGA_CLK : IN std_logic;
    LRESET_n : IN std_logic;
    LHOLD : IN std_logic;
    LHOLDA : OUT std_logic
    );
    END COMPONENT;

    --Inputs
    SIGNAL FPGA_CLK : std_logic := '0';
    SIGNAL LRESET_n : std_logic := '0';
    SIGNAL LHOLD : std_logic := '0';

    --Outputs
    SIGNAL LHOLDA : std_logic;

    signal RESET : std_logic := '1';

    type State_Type is (S0,S1,S2,S3,S4);
    signal Current_State, Next_State : State_Type;



    BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut: cdeout PORT MAP(
    FPGA_CLK => FPGA_CLK,
    LRESET_n => LRESET_n,
    LHOLD => LHOLD,
    LHOLDA => LHOLDA
    );

    FPGA_CLK <= not FPGA_CLK after 30.303 ns;
    RESET <= '0' after 303.03 ns;

    -- process
    -- begin
    --
    -- wait for 211 ns;
    -- LHOLD <= '1';
    --
    -- wait;
    --
    -- end process;
    --
    Sync: PROCESS( FPGA_CLK, RESET)
    begin

    if (RESET = '1') then
    current_state <= S0;
    elsif (rising_edge(FPGA_CLK)) then
    current_state <= next_state;
    end if;

    end process;

    Comb: PROCESS(Current_State)
    begin

    case Current_State is

    when S0 =>
    LRESET_n <= '0';
    next_state <= S1;

    when S1 =>
    LRESET_n <= '1';
    next_state <= S2;

    when S2 =>

    LHOLD <= '1';
    next_state <= S3;

    when S3 =>
    next_state <= S4;


    when S4 =>

    next_state <= S3;

    end case;

    end process;

    END;
    , Sep 22, 2005
    #1
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  2. Guest

    Some additional information:

    LHOLDA should go active on the next rising clock edge after LHOLD is
    set. This works fine in the Behav sim. In the Post P&R sim, LHOLDA
    stays low all the time.

    Joel
    , Sep 22, 2005
    #2
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  3. wrote:

    > LHOLDA should go active on the next rising clock edge after LHOLD is
    > set. This works fine in the Behav sim. In the Post P&R sim, LHOLDA
    > stays low all the time.


    I think the problem is in your Post P&R testbench.
    But a post route sim is unnecessary.

    Your RTL code is inexplicable but I see no errors.
    See a single process version of the same description below:

    -- Mike Treseler

    _____________________________

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.numeric_std.all;

    entity CDEout is
    port (
    CLK : in std_logic;
    LRESET_n : in std_logic;
    LHOLD : in std_logic;
    LHOLDA : out std_logic -- alt des. int
    );
    end CDEout;

    architecture RTL of CDEout is
    begin
    one : process(CLK, LRESET_n) is
    subtype phase_t is natural range 0 to 3; -- two bits
    variable phase_v : phase_t;
    constant active_phase_c : phase_t := 1;
    constant roll_phase_c : phase_t := 2;
    variable lholda_v : std_logic;
    begin
    template : if (LRESET_n = '0') then
    phase_v := 0;
    lholda_v := '0';
    elsif (rising_edge(CLK)) then
    if phase_v = active_phase_c then
    if lhold = '0' then
    lholda_v := '0';
    phase_v := 0;
    else
    lholda_v := '1';
    end if;
    end if;
    if phase_v < roll_phase_c then
    phase_v := phase_v + 1;
    else
    phase_v := 1; -- 0,1,2,1,2,...
    end if;
    end if template;
    lholda <= lholda_v;
    end process one;
    end architecture RTL;


    -- vsim cdeout_tb_vhd -do "add wave -r *; add wave
    /cdeout_tb_vhd/uut/one/*;run 900;"
    Mike Treseler, Sep 23, 2005
    #3
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