Problem with clock

Discussion in 'VHDL' started by aimendj, Feb 12, 2009.

  1. aimendj

    aimendj

    Joined:
    Feb 12, 2009
    Messages:
    4
    Hello,

    I'm working VHDL project. the problem is that the FPGA Frequency is not sufficient (Delay problem) so the solution is either:
    -3 Prallel instrunction for each clock edge ==> complexity*3
    -divide the clock by 3 ==> same complexity.

    i think that the second solution is better but the problem is this suitable for the FPGA and is there any limit when dividing the clock?

    Thanks for Help,
    Aymen
    ODCOM Technologies
    aimendj, Feb 12, 2009
    #1
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