problem with code for random number generation

Discussion in 'VHDL' started by sandeep_sp7, Apr 12, 2007.

  1. sandeep_sp7

    sandeep_sp7

    Joined:
    Apr 12, 2007
    Messages:
    2
    i am having a code for random number generation whose syntax is right and wh
    ich can be simulated in modelsim...but the problem is, it is not synthesising
    ..it is giving an error message as

    FATAL_ERROR:HDLParsers:vhptype.c:172:$Id: vhptype.c,v 1.6 2001/10/12 21:32:28 weilin Exp $:200 - I
    NTERNAL ERROR... while parsing E:/a/a.vhdl line 1. Contact your hot line. Process will terminate
    . To resolve this error, please consult the Answers Database and other online resources at h
    ttp://support.xilinx.com. If you need further assistance, please open a Webcase by clic
    king on the "WebCase" link at http://support.xilinx.com

    the code is:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use ieee.math_real.all; -- for UNIFORM, TRUNC
    use ieee.numeric_std.all; -- for TO_UNSIGNED

    -- Uncomment the following lines to use the declarations that are
    -- provided for instantiating Xilinx primitive components.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity trial is
    Port ( clk:in std_logic;
    sd1 : in std_logic;
    sd2 : in std_logic;
    y : out std_logic_vector(15 downto 0));
    end trial;

    architecture Behavioral of trial is

    signal clk_div:std_logic;
    begin
    process(clk)
    variable clk_vec:std_logic_vector(11 downto 0):=(others=>'0');
    begin
    if(clk'event and clk='1')
    then clk_vec:=clk_vec+'1';
    end if;
    clk_div<=clk_vec(11);

    end process;





    process(clk_div)

    -- Seed values for random generator
    variable seed1, seed2: positive;
    -- Random real-number value in range 0 to 1.0
    variable rand: real;
    -- Random integer value in range 0..4095
    variable int_rand: integer;
    -- Random 12-bit stimulus
    variable stim: std_logic_vector(15 downto 0);


    begin

    -- initialise seed1, seed2 if you want -
    -- otherwise they're initialised to 1 by default
    --loop -- testbench stimulus loop?
    UNIFORM(seed1, seed2, rand);
    -- get a 12-bit random value...
    -- 1. rescale to 0..(nearly)4096, find integer part
    int_rand := INTEGER(TRUNC(rand*65536.0));
    -- 2. convert to std_logic_vector
    stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));
    y<=stim;
    --end loop;
    end process;

    end Behavioral;

    does anyone have a solution to this problem!!!!!!!!!!
    plssss post the correct code.
     
    sandeep_sp7, Apr 12, 2007
    #1
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