Problem with frequency divider

Discussion in 'VHDL' started by mcholbi, May 30, 2011.

  1. mcholbi

    mcholbi

    Joined:
    May 30, 2011
    Messages:
    2
    Hello!

    I have been working with this frequency divider a long time:

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;

    ENTITY frecuency_divider IS
    GENERIC(INPUTPERIOD : IN integer := 10; -- 10 ns
    OUTPUTPERIOD : IN integer := 5000); -- 1000 ns
    PORT( i_reset : IN STD_LOGIC;
    i_clk : IN STD_LOGIC;
    o_clk : OUT STD_LOGIC);
    END frecuency_divider;

    ARCHITECTURE behavioral OF frecuency_divider IS
    SIGNAL s_count : INTEGER RANGE 1 TO (OUTPUTPERIOD/INPUTPERIOD);
    BEGIN
    p_countercontrol: PROCESS (i_reset, i_clk)
    BEGIN
    IF i_reset = '0' THEN
    s_count <= 1;
    ELSIF rising_edge(i_clk) THEN
    IF s_count < (OUTPUTPERIOD/INPUTPERIOD) THEN
    s_count <= s_count + 1;
    ELSE
    s_count <= 1;
    END IF;
    END IF;
    END PROCESS;

    p_clock : PROCESS (i_reset, s_count)
    BEGIN
    IF i_reset = '0' THEN
    o_clk <= '0';
    ELSIF s_count <= (OUTPUTPERIOD/INPUTPERIOD)/2 THEN
    o_clk <= '0';
    ELSE
    o_clk <= '1';
    END IF;
    END PROCESS;
    END behavioral;

    It works fine in simulation but in post-synthesis simulation (and on the real board) it provokes some edges no desired in the middle of the low phase:

    [​IMG]

    Does anyone have any idea why can it happen?

    Thanks a lot for your help!!!!
    mcholbi, May 30, 2011
    #1
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  2. mcholbi

    vcraft

    Joined:
    Feb 14, 2011
    Messages:
    7
    It looks strange, really.
    Me I would start from the second process.
    In general, playing with reset line like a normal signal is asking for trouble.
    It MAY cause some perturbations sometimes.

    Why not to make it a real register to prevent glitches btw???
    Just to be sure ...

    p_clock : PROCESS (i_reset, i_clk)
    BEGIN
    IF i_reset = '0' THEN
    o_clk <= '0';
    ELSIF i_clk'event and i_clk = '1' then
    if s_count <= (OUTPUTPERIOD/INPUTPERIOD)/2 THEN
    o_clk <= '0';
    ELSE
    o_clk <= '1';
    END IF;
    END IF;
    END PROCESS;
    vcraft, May 31, 2011
    #2
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  3. mcholbi

    mcholbi

    Joined:
    May 30, 2011
    Messages:
    2
    It worked!

    A thousand thanks vcraft, this solved this annoying behaviour :D

    and I think a lot of problems I had, thanks a lot!!!
    mcholbi, May 31, 2011
    #3
  4. mcholbi

    vcraft

    Joined:
    Feb 14, 2011
    Messages:
    7
    Thanks for feedback information.

    As I said, this one shall be classified among the "asking for trouble" ones rather than "bad".
    It is always interesting to see proved case of trouble in real hardware caused by this kind of vilolation.

    cheers
    vcraft

    vcraft, Jun 7, 2011
    #4
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