V
Vipin
Hi Guys,
I am a graduate student at University of Missouri - Rolla. I have been
working with one of my project "RISC processor design using VHDL". I
had to design the processor in vhdl and simulate it and test using
mentor graphics tools. I have completed the design and simulation and
is working fine.
The problem came when I was trying to move to the layout stage using IC
station tool from mentor graphics. Following are the steps I took for
the complete design process:
" VHDL description of RISC processor.
o 21 files in all, three level hierarchy, the top file: CPU.vhd
" VHDL synthesis using spectrum tool.
o I got 3500 gates in all for the final design (not transistors).
o I verified the post synthesis vhd file and is working fine.
" The layout process (here I get started with the problems).
o I convert the edif file I get from spectrum tool to eddm file using
"edif2eddm" script.
o I create the required viewpoints using adk_dve script.
o I create the layout using IC STATION automated layout technique.
o I get more than 300 DRC errors and some 200 overflows unconnected.
I tried ami05 and tsmc035 with following results:
with ami05: 300 DRC errors and 200 overflows undone.
With tsmc035: 250DRC errors and 20 overflows undone.
I don't understand why IC station is not able to route all the
overflows. One more frustrating point is that the IC station is itself
creating DRC errors on its own. As I am using automated layout
technique, it should route according to the DRC rules for the
corresponding technology.
I would really appreciate any kind of help in this regard.
Thanks in advance.
VIPIN SHARMA.
Graduate Student,
University of Missouri - Rolla.
I am a graduate student at University of Missouri - Rolla. I have been
working with one of my project "RISC processor design using VHDL". I
had to design the processor in vhdl and simulate it and test using
mentor graphics tools. I have completed the design and simulation and
is working fine.
The problem came when I was trying to move to the layout stage using IC
station tool from mentor graphics. Following are the steps I took for
the complete design process:
" VHDL description of RISC processor.
o 21 files in all, three level hierarchy, the top file: CPU.vhd
" VHDL synthesis using spectrum tool.
o I got 3500 gates in all for the final design (not transistors).
o I verified the post synthesis vhd file and is working fine.
" The layout process (here I get started with the problems).
o I convert the edif file I get from spectrum tool to eddm file using
"edif2eddm" script.
o I create the required viewpoints using adk_dve script.
o I create the layout using IC STATION automated layout technique.
o I get more than 300 DRC errors and some 200 overflows unconnected.
I tried ami05 and tsmc035 with following results:
with ami05: 300 DRC errors and 200 overflows undone.
With tsmc035: 250DRC errors and 20 overflows undone.
I don't understand why IC station is not able to route all the
overflows. One more frustrating point is that the IC station is itself
creating DRC errors on its own. As I am using automated layout
technique, it should route according to the DRC rules for the
corresponding technology.
I would really appreciate any kind of help in this regard.
Thanks in advance.
VIPIN SHARMA.
Graduate Student,
University of Missouri - Rolla.