# problem with if statement

Discussion in 'VHDL' started by ledinhkha@gmail.com, Dec 17, 2005.

1. ### Guest

hi all,
i got problem with my if statement. Here is my code

temp <= X"1A";

if ((X"1A" <= temp) and (X"1E" >= temp)) then
k <= X"002";
elsif ((X"1F" <= temp) and (X"23" >= temp)) then
k <= X"003";
elsif ((X"24" <= temp) and (X"28" >= temp)) then
k <= X"004";
else
k <= X"005";
end if;

then k is X"005", not like X"002" as I want. Is there anyone here can
explain why the result is like that? Do we have to notice anything with
if statement?
Thks
Kha

, Dec 17, 2005

2. ### ZaraGuest

On 16 Dec 2005 23:04:09 -0800, wrote:

>hi all,
>i got problem with my if statement. Here is my code
>
>temp <= X"1A";
>
>if ((X"1A" <= temp) and (X"1E" >= temp)) then
> k <= X"002";
>elsif ((X"1F" <= temp) and (X"23" >= temp)) then
> k <= X"003";
>elsif ((X"24" <= temp) and (X"28" >= temp)) then
> k <= X"004";
>else
> k <= X"005";
>end if;
>
>then k is X"005", not like X"002" as I want. Is there anyone here can
>explain why the result is like that? Do we have to notice anything with
>if statement?
>Thks
>Kha

May you show us a little more? In particular, temp declaration.

*Because* you may be assigning an 8 bit vector ("1A") to some vector
of a different dimension, which may be valid (and may also generate
some kind of warning!).

But later you are comparing temp to an 8 bit vector. And this
comparison has no sense at all if temp has a length different from 8
bits, so you might get the result you get. Or anything.

Regards

Zara

Zara, Dec 17, 2005

3. ### Guest

Thks Zara, for your reply. And here is my declaration:

signal k: std_logic_vector(11 downto 0);
signal temp: std_logic_vector(7 downto 0);

I think it is OK, but i don't know why it always drop into the last
case.
Thks
Kha

, Dec 17, 2005
4. ### Mike TreselerGuest

wrote:

> then k is X"005", not like X"002" as I want.

If you make temp a variable,
this will work like you expect.

-- Mike Treseler

Mike Treseler, Dec 17, 2005
5. ### Eric SmithGuest

writes:
> temp <= X"1A";
>
> if ((X"1A" <= temp) and (X"1E" >= temp)) then
> k <= X"002";
> elsif ((X"1F" <= temp) and (X"23" >= temp)) then
> k <= X"003";
> elsif ((X"24" <= temp) and (X"28" >= temp)) then
> k <= X"004";
> else
> k <= X"005";
> end if;
>
> then k is X"005", not like X"002" as I want. Is there anyone here can
> explain why the result is like that? Do we have to notice anything with

Possibly you misunderstand the way signals work. When you assign a
new value to a signal (e.g., temp <= X"1A"), that doesn't change the
value of the signal "now". It schedules a change for some future time.
If no explicit time is given, the change occurs on the next delta time.

So if your assignment to temp and your conditionals are in a process and
being simulated on the same delta, the value the conditionals will see
for temp will be the old value.

If you advance to the next simuluation delta time, temp will have the
value you expect, and the conditional will work as you expect.

Remember, signals aren't variables. Signals represent a physical signal,
and can't change instantaneously. They take at least one delta time
to change. If you aren't using temp to model an electrical signal, then
you probably want it to be a variable rather than a signal.

Note that a simulation delta time is arbitrarily smaller than any time
unit you can designate, so in terms of measurable time it is
conceptually instantaneous, but in terms of simulation the next delta
time is always later, not "now".

Eric Smith, Dec 17, 2005
6. ### Guest

thks very much for your answer. I think that's my problem. I will try
to use variable.

, Dec 17, 2005
7. ### Guest

thks Eric, Zara and Mike!
I change the order of checking my signal (after a clock, not right
after setting it as before), and it worked well. Now I understood about
signal.
Thks and have a nice weekend to all!
Kha

, Dec 18, 2005