Problem with JTAG_SIM_VIRTEX4

Discussion in 'VHDL' started by Stefan Hauf, May 15, 2006.

  1. Stefan Hauf

    Stefan Hauf Guest

    Hello,

    i have a problem using the JTAG_SIM_VIRTEX4 block from Xilinx. I am
    able to send data to the BSCAN block in the design but cannot readout
    data from the BSCAN block. I discoverd that the jtag_instruction_name
    is set to IDCODE in the beginning, after shifting some bits into the
    register always switches to UNKNOWN.
    Did anyone use this function successfully?

    BR Stefan
     
    Stefan Hauf, May 15, 2006
    #1
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  2. Stefan Hauf

    Stefan Hauf Guest

    Hi,

    I solved the probem on my own.
    In the unisim source i found the pattern (14bit) to get in the right
    state. In the application note only the last 5 bits are mentioned.

    BR
    Stefan
     
    Stefan Hauf, May 15, 2006
    #2
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