Problem with loop

Discussion in 'VHDL' started by Winkiel, Jan 3, 2004.

  1. Winkiel

    Winkiel Guest

    Hi!

    I've got a problem with my project.
    It will be a function like lpm_clshift.
    I don't know what's wrong and how to fix it. Please help!

    The compiler(MaxPlus+2) throws error:
    "Unsupported feature error: a deffered constant declaration
    without a full declaration is not supported".

    Thank you, Winkiel.

    Its a part of my file - enough to show the problem:

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;

    ENTITY shifting IS
    GENERIC(DL: INTEGER := 8;
    ODL: INTEGER := 3);
    PORT (data: IN STD_LOGIC_VECTOR(DL-1 DOWNTO 0);
    typeof: STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
    result: BUFFER STD_LOGIC_VECTOR(DL-1 DOWNTO 0);
    underflow, overflow: OUT STD_LOGIC);
    END;

    ARCHITECTURE arch OF shifting IS
    SIGNAL tab: STD_LOGIC_VECTOR(ODL*(DL-1) DOWNTO 0);
    BEGIN
    PROCESS
    VARIABLE v: INTEGER RANGE 0 TO DL-1 := 0;
    BEGIN
    tab(DL-1 DOWNTO 0) <= data;
    v:= 1;
    IF (typeof = "00") THEN
    l1:FOR i IN 1 TO ODL-1 LOOP -- I think problem is
    right here inside this loop
    tab(((i+2)*(DL-1)-v) DOWNTO (i+1)*(DL-1)) <=
    tab(((i+1)*(DL-1)+1) DOWNTO (i*(DL-1)-v));
    v:=v*2;
    END LOOP l1;
    result <= tab(ODL*(DL-1) DOWNTO (ODL-1)*(DL-1));
    END IF;
    underflow <= '0';
    overflow <= '0';
    END PROCESS;
    END arch;

    --
    Winkiel
    "Expect The Unexpected"
    Winkiel, Jan 3, 2004
    #1
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