problem with model-sim altera eda in quartus

[ulla]

i want to simulate my design with the in-built simulator model-sim altera
in quartus. i can do the full compilation until the eda-netlist writer
without any problems but then i get the following errors and infos and i
really don't know what to do and would be very happy for useful hints.
cheers ulla


Info: Running Quartus II Shell
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Thu Sep 2 17:31:14 2004
Info: Command: quartus_sh -t /tools/quartus/4.1/linux/qnativesim.tcl hello
hello
Info: quartus(args): hello hello
Info: Start Nativelink Simulation process
Info: Initialization of EDA simulation settings was successful
Info: Changed to directory simulation/modelsim ...
Info: Current directory is : /home/ulla/simulation/modelsim
Info: Running ModelSim-Altera software
Info: VHDL script : /tools/quartus/4.1/linux//modelsim_vhdl.tcl
Info: Initialization of NativeLink successful
Info: Initialization of EDA advanced simulation settings was successful
Info: Creating directory modelsim_work for VHDL simulation
Info: Compiling design file hello.vho
Error: Compilation of design file hello.vho was NOT successful
Info: ModelSim: couldn't execute "vcom": no such file or directory
Info: Compiling test bench file
/home/ulla/simulation/modelsim/myTestbench1.vht
Error: Compilation of test bench file
/home/ulla/simulation/modelsim/myTestbench1.vht was NOT successful
Info: ModelSim: couldn't execute "vcom": no such file or directory
Info: Simulating design TB_CARD
Error: Simulation of design TB_CARD was NOT successful
Info: ModelSim: couldn't execute "vsim": no such file or directory
Info: Check ModelSim transcript file for more details
Error: NativeLink simulation flow was NOT successful
Info: Nativelink simulation process ended
Error: Quartus II Full Compilation was unsuccessful. 1 error, 188
warnings

 

[ALuPin]

Hi,

do you want to perform a functional simulation
1) of your VHDL code or
2) of the gate-level (synthesized netlist from Quartus) file?

Did you simulate the behaviour of your design that is number 1) ?
This kind of simulation is recommended to verify the functionality
of your design.
You do not need to let QuartusII open Modelsim automatically, just
deactivate (under Settings --> Simulation) "Run tool automatically".
I also work with QuartusII and Modelsim (by the way: What versions
do you use?) and I always start Modelsim separately.

Kind regards

André

 

[Mike Treseler]

i want to simulate my design with the in-built simulator model-sim altera
in quartus.

Info: Creating directory modelsim_work for VHDL simulation
Info: Compiling design file hello.vho
Error: Compilation of design file hello.vho was NOT successful
Info: ModelSim: couldn't execute "vcom": no such file or directory
Info: Compiling test bench file
/home/ulla/simulation/modelsim/myTestbench1.vht
Error: Compilation of test bench file
/home/ulla/simulation/modelsim/myTestbench1.vht was NOT successful

Sounds like vcom is not in your path.

Open a shell (or start, run, command) and type "vcom"
If it's not in your path you will get something like:

62 steptoe Thu Sep 02 /evtfs/home/tres/vhdl > vcom
bash: vcom: command not found

Once you get the path set, expect this:

63 steptoe Thu Sep 02 /evtfs/home/tres/vhdl > vcom
Usage: vcom [options] files
Options:
-help Print this message
-time Print the compilation wall clock time
-version Print the version of the compiler
- ...

I like to use vcom and vsim interactively
while I'm editing code. Altera pushes a
synthesis-first flow that makes no sense
to me. In any case, I hesitate to automate
a process that I haven't done manually first.

Maybe one of the Altera guys will comment.

-- Mike Treseler

 

[ulla]

hi andre, thank you for your answer.

I want to simulate the behaviour of my design and I don't know how to do
it properly with quartus(4.1).

thanks
ulla

 

[ALuPin]

hi andre, thank you for your answer.

I want to simulate the behaviour of my design and I don't know how to do
it properly with quartus(4.1).

thanks
ulla

Hi Ulla,

did you have experience in writing testbenches for functional simulation ?

Rgds
André

 

[ulla]

Hi Andre,

yes I know how to write proper testbenches for functional simulations. I
normally used synopsys VCC for simulation purposes and as I don't have the
possibility to use it anymore, I have to use Quartus.

Rgds
Ulla

 

[Ajeetha Kumari]

Hi Ulla,
I think Quatrus is a synthesis tool and not a simulator. If you
are looking for a free simulator, try ModelsimXE (from xilinx.com) or
Icarus Verilog.

Good Luck,
Aji,
http://www.noveldv.com

 

[ulla]

Hi Aji,

thanks for the recommendation. I will try it.
Ulla

 

[ALuPin]

Hi Andre,

yes I know how to write proper testbenches for functional simulations. I
normally used synopsys VCC for simulation purposes and as I don't have the
possibility to use it anymore, I have to use Quartus.

Rgds
Ulla

Hi Ulla,

are you using QuartusII WebEdition or with full license including Modelsim?

You should use an independent simulation tool for your simulations and
as I use Modelsim I can recommend it ;o)

Rgds
Andre