Problem with post-route simulation / timing simulation

Discussion in 'VHDL' started by jasperng, Nov 27, 2008.

  1. jasperng

    jasperng

    Joined:
    Oct 8, 2008
    Messages:
    4
    Hi there, I tried to run my design using modelsim through Xilinx ISE, However it seems i keep encountering this problem. Can anyone know what isthe problem and how to fix this ? ... It seems to be missing a library named simprim. But I have no idea how to get the library and implement it ? ...

    Help is appreciated thanks.

    # -- Loading package standard
    # -- Loading package std_logic_1164
    # ** Error: (vcom-19) Failed to access library 'simprim' at "simprim".
    # No such file or directory. (errno = ENOENT)
    # ** Error: C:/FPGAdv71LSPS/Modeltech/win32/vcom failed.
    # Error in macro ./tb_TopLevelRS232.tdo line 6
    # C:/FPGAdv71LSPS/Modeltech/win32/vcom failed.
    # while executing
    # "vcom -explicit -93 "netgen/par/TopLevelRS232_timesim.vhd""
    jasperng, Nov 27, 2008
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Drew
    Replies:
    0
    Views:
    454
  2. chaitu
    Replies:
    3
    Views:
    941
    Brian Drummond
    May 30, 2007
  3. jonasmaes@gmail.com

    RS232 post-route simulation issues

    jonasmaes@gmail.com, Oct 7, 2007, in forum: VHDL
    Replies:
    3
    Views:
    560
    jonasmaes@gmail.com
    Oct 7, 2007
  4. sridar

    Post Route Simulation

    sridar, Jun 23, 2008, in forum: VHDL
    Replies:
    0
    Views:
    478
    sridar
    Jun 23, 2008
  5. Bar Nash

    POST PLACE and ROUTE SIMULATION

    Bar Nash, Oct 6, 2008, in forum: VHDL
    Replies:
    2
    Views:
    881
    Kim Enkovaara
    Oct 6, 2008
Loading...

Share This Page