Problem with shift operation

Discussion in 'VHDL' started by Chandru.Kundagol@gmail.com, Apr 21, 2006.

  1. Guest

    I hav the follwoing simple code which does left shifting operation.

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;
    entity counter is
    port (
    q: inout STD_LOGIC_VECTOR (3 downto 0);
    clock: in STD_LOGIC;
    reset: in STD_LOGIC;
    en: in STD_LOGIC
    );
    end counter;



    architecture counter of counter is
    signal count:std_logic_vector(3 downto 0):="0000";
    begin

    process(clock,reset)
    begin

    if reset='0' then
    count<="0000";
    elsif(clock='1') then
    if en='1' then

    l1: for i in 1 to 3 loop
    count(i)<=q(i-1);
    end loop l1;
    count(0)<='0';

    else
    count<=q;
    end if;
    end if;
    end process;
    q<=count; -- The q value is not getting updated
    with the count value.
    end counter;

    The problem with this code is that the q(port) value is not getting
    updated with count value,though count gets updated.I did single step
    execution,i see the statement q<=count being executed.I used the tool
    Active HDL 4.2.PLEASE HELP....
    , Apr 21, 2006
    #1
    1. Advertising

  2. KJ Guest

    Move the "q<=count;" statement outside of the process.

    i.e..
    process
    .....
    end process;

    q<=count;

    KJ

    <> wrote in message
    news:...
    >I hav the follwoing simple code which does left shifting operation.
    >
    > library IEEE;
    > use IEEE.std_logic_1164.all;
    > use IEEE.std_logic_unsigned.all;
    > entity counter is
    > port (
    > q: inout STD_LOGIC_VECTOR (3 downto 0);
    > clock: in STD_LOGIC;
    > reset: in STD_LOGIC;
    > en: in STD_LOGIC
    > );
    > end counter;
    >
    >
    >
    > architecture counter of counter is
    > signal count:std_logic_vector(3 downto 0):="0000";
    > begin
    >
    > process(clock,reset)
    > begin
    >
    > if reset='0' then
    > count<="0000";
    > elsif(clock='1') then
    > if en='1' then
    >
    > l1: for i in 1 to 3 loop
    > count(i)<=q(i-1);
    > end loop l1;
    > count(0)<='0';
    >
    > else
    > count<=q;
    > end if;
    > end if;
    > end process;
    > q<=count; -- The q value is not getting updated
    > with the count value.
    > end counter;
    >
    > The problem with this code is that the q(port) value is not getting
    > updated with count value,though count gets updated.I did single step
    > execution,i see the statement q<=count being executed.I used the tool
    > Active HDL 4.2.PLEASE HELP....
    >
    KJ, Apr 21, 2006
    #2
    1. Advertising

  3. kunal Guest

    u can try with variable. then it will update imediatly.
    u can shif left like
    temp := temp(2 downto 0) & data.
    yhrough u can roatate also. it is easier than for loop.
    kunal, Apr 24, 2006
    #3
  4. jens Guest

    Are you sure you want a latch instead of a flip-flop? I assume not, in
    which case replace

    elsif(clock='1') then

    with

    elsif rising_edge(clock) then

    and then everything should work better.
    jens, Apr 24, 2006
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Roberto Gallo

    Shift - byte[] buf shift

    Roberto Gallo, Jan 27, 2004, in forum: Java
    Replies:
    3
    Views:
    2,045
    Thomas Schodt
    Jan 27, 2004
  2. Wenjie
    Replies:
    3
    Views:
    1,031
    Ron Samuel Klatchko
    Jul 11, 2003
  3. Santosh Nayak

    Left Shift / Right Shift Operators

    Santosh Nayak, Nov 30, 2006, in forum: C Programming
    Replies:
    16
    Views:
    1,446
    CBFalconer
    Nov 30, 2006
  4. Sanny
    Replies:
    38
    Views:
    3,378
    Thomas Richter
    Apr 29, 2011
  5. devphylosoff

    what "shift" does, if not "$_ = shift;" ?

    devphylosoff, Nov 29, 2007, in forum: Perl Misc
    Replies:
    3
    Views:
    325
    Michele Dondi
    Dec 4, 2007
Loading...

Share This Page