Problem With Signed Number in Vhdl

[mohammadyou]

hi
i am newbie in vhdl
when i want compare signed Number in vhdl
i cant get true answer
my code is :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.signed;

entity test_compare is
end test_compare;

architecture Behavioral_Fl of test_compare is
type Bound_of_Function is Array (0 to 2) of signed (15 downto 0);
constant Bound_Data : Bound_of_Function :=(x"FFF6",x"0000",x"000A");
signal Net_Test : signed (15 downto 0);
signal Output :   STD_LOGIC_VECTOR (15 downto 0);
begin
sim: process 
begin
    Net_Test<= x"FFF5"; -- -11
  wait for 100ns;  
    Net_Test<= x"FFF6"; -- -10
  wait for 100ns;
    Net_Test<= x"0000";  -- 0
  wait for 100ns;
    Net_Test<= x"000B"; -- 10
  wait for 100ns;
end process; 

Fl:process(Net_Test)
    begin
     if (Net_Test < (Bound_Data(0))) then 
         Output <= (x"7FFF");
     elsif (Net_Test < (Bound_Data(1))) then 
         Output <= std_logic_vector(Bound_Data(1));
     elsif (Net_Test < (Bound_Data(2))) then
         Output <= std_logic_vector(Bound_Data(2)); 
     elsif (Net_Test >= (Bound_Data(2))) then  
         Output <= (x"8000"); 
     end if;
   end process;
end Behavioral_Fl;

when Net_Test=0x"FFF6" (-10 < 0 ) i expected Output =x"0000" but
output =x"8000" !!
output of my code is:

images.elektroda.net/95_1293235188.jpg

where is my problem? :-x
thank you

 

[bmackin]

Library is wrong

If you use the library statements:

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
-- use IEEE.NUMERIC_STD.signed;

it works as you would expect it to.

By the way, you have one other error/typo:

Net_Test<= x"000B"; -- 10

Hex B is 11, not 10.