problem with simulating a program

Discussion in 'VHDL' started by DG, Oct 10, 2003.

  1. DG

    DG Guest

    Hi,

    First I apalogize because my question is probably stupid but I am trying to
    learn VHDL by writing very basic programs but I have a problem with the
    follwing one

    I want to simulate the following peace of code (I have no problem with that
    code) :
    ------------------------
    Library ieee;
    Use ieee.std_logic_1164.all;
    Use ieee.numeric_std.all;
    Use ieee.std_logic_unsigned.all;

    entity CMP4BITS is
    PORT (
    CLOCK : in std_logic;
    Q : inout std_logic_vector(3 downto 0));
    end CMP4BITS;

    architecture DESCRIPTION of CMP4BITS is
    begin
    process (CLOCK)
    begin
    if (CLOCK ='1' and CLOCK'event) then
    Q <= Q + 1;
    end if;
    end process;
    end DESCRIPTION;
    ------------------------

    My problem is with the program in charge to launch the simulation of the
    code above; which is:
    ------------------------
    Library ieee;
    Use ieee.std_logic_1164.all;

    ENTITY test_cmpt IS
    END test_cmpt;

    ARCHITECTURE behavior OF test_cmpt IS
    COMPONENT cmp4bits
    PORT (CLOCK : in std_logic;
    Q : inout std_logic_vector(3 downto 0));
    END COMPONENT;

    SIGNAL CLOCK : std_logic;
    SIGNAL Q : std_logic_vector(3 downto 0);

    BEGIN
    DUT: cmp4bits PORT MAP (CLOCK, Q);

    stimulus: PROCESS
    BEGIN
    CLOCK <= '0';
    wait for 100 ns;

    CLOCK <= '1';
    wait for 100 ns;
    END PROCESS;
    END behavior;
    ------------------------

    Actually the problem is when I launch the simulation all the values of Q are
    X (which means undetermined) and after having executed "Q <= Q + 1", Q is
    always undetermined and so son. I guess one solution would be to initialize
    Q before the execution of "cmp4bits", but I don't know how... Obviously I
    tried to put an "Q <= "0000" before "CLOCK <= '0'" but it had no effects.

    If someone had an idea, do not hesitate to suggest :).

    Regards
     
    DG, Oct 10, 2003
    #1
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  2. DG

    MM Guest

    There are many ways to solve your problem. Any particular reason why Q
    should be bidirectional? Anyways, here is the code that works (as you can
    see I corrected the module, not the test bench):

    Library ieee;
    Use ieee.std_logic_1164.all;
    --Use ieee.numeric_std.all;
    Use ieee.std_logic_unsigned.all;

    entity CMP4BITS is
    PORT (
    CLOCK : in std_logic;
    Q : inout std_logic_vector(3 downto 0));
    end CMP4BITS;

    architecture DESCRIPTION of CMP4BITS is
    begin

    process (CLOCK)
    variable cnt : std_logic_vector(3 downto 0):=X"0"; -- the
    initialization happens here
    begin
    if (CLOCK ='1' and CLOCK'event) then
    cnt := cnt + 1;
    end if;
    Q <= cnt;
    end process;

    end DESCRIPTION;

    The above is OK for simulation, but in real life you will most likely want
    to add a reset signal to your counter, something lke this:

    process (CLOCK, RST_N)
    begin
    if RST_N='0' then
    Q <= (others=>'0');
    if (CLOCK ='1' and CLOCK'event) then
    Q <= Q + 1;
    end if;
    end process;

    /Mikhail
     
    MM, Oct 11, 2003
    #2
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  3. DG

    MM Guest

    > Q : inout std_logic_vector(3 downto 0));

    I should have added why I asked about Q being bidirectional. The reason you
    can't initialize Q from the test bench is because it is being driven by the
    module all the time, so you have a bus conflict because a bidirectional bus
    can't be driven by 2 drivers at the same time and be in a determined state
    provide both drivers are of equal strength. In other words, I think you
    should change your Q to be a simple output... That is unless you have a
    valid reason for it to be bidirectional, but if that's the case it is a
    different topic...

    /Mikhail
     
    MM, Oct 11, 2003
    #3
  4. DG

    DG Guest

    "MM" <> a écrit dans le message de
    news:bm83am$j9vp1$-berlin.de...
    > > Q : inout std_logic_vector(3 downto 0));

    >
    > I should have added why I asked about Q being bidirectional. The reason

    you
    > can't initialize Q from the test bench is because it is being driven by

    the
    > module all the time, so you have a bus conflict because a bidirectional

    bus
    > can't be driven by 2 drivers at the same time and be in a determined state
    > provide both drivers are of equal strength. In other words, I think you
    > should change your Q to be a simple output... That is unless you have a
    > valid reason for it to be bidirectional, but if that's the case it is a
    > different topic...


    Thank you Mikhail for your help, you had solved my problem.

    You are right, I don't need at all to make Q bidirectional if I had a RST
    signal which allow me to reset my counter in the test driver. This is
    exactly what I was looking for....

    Best Regards.
     
    DG, Oct 11, 2003
    #4
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