Problem with single bit slv

S

salman sheikh

Hello,

I am creating a generic width latch. When using it to create a single
bit, I run into elaboration warnings in Modelsim (which may give problem
during synthesis, I suspect? The problem seems to be when instantiating
a single bit latch standard logic_vector (0 downto 0) and connecting
signals from a higher level that are signals of std_logic. It seems to
me that it would be a real pain to change all the higher level signals
to slv(0 downto 0) or another pain is to create a separate single bit
(non-generic) latch component for those places where needed. Any
suggested solutions to make this warning go away?

Thanks in advance for any help.


Salman Sheikh
 
J

Just an Illusion

Hi Salman,

Your error is certainly link to mismatch of type (std_logic <>
std_logic_vector).
When you call your module, first convert your std_logic into an
std_logic_vector.
To do use std_logic_arith and function conv_std_logic_vector.

Bye,
JaI
 
A

Allan Herriman

Hello,

I am creating a generic width latch. When using it to create a single
bit, I run into elaboration warnings in Modelsim (which may give problem
during synthesis, I suspect? The problem seems to be when instantiating
a single bit latch standard logic_vector (0 downto 0) and connecting
signals from a higher level that are signals of std_logic. It seems to
me that it would be a real pain to change all the higher level signals
to slv(0 downto 0) or another pain is to create a separate single bit
(non-generic) latch component for those places where needed. Any
suggested solutions to make this warning go away?

you seem to be trying this in your port map:

slv_port => sl_signal,

and it's not working because of the type clash.

Instead, try this:

slv_port(0) => sl_signal,

Regards,
Allan.
 

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