A
Andreas Wallner
Hi,
I have a problem with a piece of code I'm simulating using modelsim.
The piece of code should allow sending a strobe from one clock domain
to another.
-- snip --
library ieee;
use ieee.std_logic_1164.all;
entity strobe_handshake is
port (
-- clk domain A
clka : in std_ulogic;
reqa : in std_ulogic;
siga : out std_ulogic;
-- clk domain B
clkb : in std_ulogic;
reqb : in std_ulogic;
sigb : out std_ulogic
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture rtl of strobe_handshake is
signal muxa : std_ulogic := '0';
signal muxb : std_ulogic := '0';
signal togglea : std_ulogic := '0';
signal toggleb : std_ulogic := '0';
signal synca : std_ulogic_vector(2 downto 0) := "000";
signal syncb : std_ulogic_vector(2 downto 0) := "000";
begin
muxa <= togglea when reqa = '0' else not togglea;
siga <= synca(2) xor synca(1);
process(clka)
begin
if clka'event and clka = '1' then
togglea <= muxa;
syncb <= syncb(1 downto 0) & toggleb;
end if;
end process;
muxb <= toggleb when reqb = '0' else not toggleb;
sigb <= syncb(2) xor syncb(1);
process(clkb)
begin
if clkb'event and clkb = '1' then
toggleb <= muxb;
synca <= synca(1 downto 0) & togglea;
end if;
end process;
end architecture;
-- snip --
ATM I just stimulate the DUT with this:
-- snip --
dut: entity work.strobe_handshake(rtl)
port map (
clka => clk1,
reqa => req1,
siga => ack1,
clkb => clk2,
reqb => req2,
sigb => ack2
);
clock_1: process
begin
clk1 <= not clk1;
wait for (1.0/55000000.0) * 1 sec;
end process;
clock_2: process
begin
clk2 <= not clk2;
wait for (1.0/100000000.0) * 1 sec;
end process;
-- snip --
The problem is: I would expect that the does not output a pulse (sig*)
line, until I input a strobe on the req* line. If the clocks in the
stimulus start with a high->low transition (@ 0 ps) everything works
as I expect it, if the stimulus starts low->high it outputs a pulse,
because the mux* line starts off high, although the start value is
defined as '0'.
Any ideas why this is?
Regards,
Andreas
I have a problem with a piece of code I'm simulating using modelsim.
The piece of code should allow sending a strobe from one clock domain
to another.
-- snip --
library ieee;
use ieee.std_logic_1164.all;
entity strobe_handshake is
port (
-- clk domain A
clka : in std_ulogic;
reqa : in std_ulogic;
siga : out std_ulogic;
-- clk domain B
clkb : in std_ulogic;
reqb : in std_ulogic;
sigb : out std_ulogic
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture rtl of strobe_handshake is
signal muxa : std_ulogic := '0';
signal muxb : std_ulogic := '0';
signal togglea : std_ulogic := '0';
signal toggleb : std_ulogic := '0';
signal synca : std_ulogic_vector(2 downto 0) := "000";
signal syncb : std_ulogic_vector(2 downto 0) := "000";
begin
muxa <= togglea when reqa = '0' else not togglea;
siga <= synca(2) xor synca(1);
process(clka)
begin
if clka'event and clka = '1' then
togglea <= muxa;
syncb <= syncb(1 downto 0) & toggleb;
end if;
end process;
muxb <= toggleb when reqb = '0' else not toggleb;
sigb <= syncb(2) xor syncb(1);
process(clkb)
begin
if clkb'event and clkb = '1' then
toggleb <= muxb;
synca <= synca(1 downto 0) & togglea;
end if;
end process;
end architecture;
-- snip --
ATM I just stimulate the DUT with this:
-- snip --
dut: entity work.strobe_handshake(rtl)
port map (
clka => clk1,
reqa => req1,
siga => ack1,
clkb => clk2,
reqb => req2,
sigb => ack2
);
clock_1: process
begin
clk1 <= not clk1;
wait for (1.0/55000000.0) * 1 sec;
end process;
clock_2: process
begin
clk2 <= not clk2;
wait for (1.0/100000000.0) * 1 sec;
end process;
-- snip --
The problem is: I would expect that the does not output a pulse (sig*)
line, until I input a strobe on the req* line. If the clocks in the
stimulus start with a high->low transition (@ 0 ps) everything works
as I expect it, if the stimulus starts low->high it outputs a pulse,
because the mux* line starts off high, although the start value is
defined as '0'.
Any ideas why this is?
Regards,
Andreas