problem with testbench

Discussion in 'VHDL' started by crazyrdx, Feb 15, 2006.

  1. crazyrdx

    crazyrdx Guest

    Dear all,

    I have been trying to test my CRC generator, but am unable to find out
    why it doesnt seem to work, the CRC value generated is always FFFFFFFF
    (for 32 bit crc). I think it could be my testbench im not sure

    could someone please help me with this

    THE CRC GENERATOR code is


    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_unsigned.all;

    entity crcGenerator is

    generic (WIDTH_BYTE : integer:=8;
    WIDTH_CRC : integer:=32
    );
    port (
    clk : in STD_LOGIC; -- Input clock
    rst : in STD_LOGIC; --
    Asynchronous active low reset
    newFrame : in STD_LOGIC; -- Assert to
    restart calculations
    newByte : in STD_LOGIC; -- Assert to
    indicate a crcValid input byte
    inByte : in STD_LOGIC_VECTOR (7 downto 0); -- Input byte
    crcValid : out STD_LOGIC; -- Indicates
    crcValid CRC. Active HIGH
    crcValue : out STD_LOGIC_VECTOR (31 downto 0) -- CRC output
    );

    end crcGenerator;




    architecture crcGenerator_arch of crcGenerator is

    signal presState : STD_LOGIC; -- current state
    constant stIdle : STD_LOGIC := '0';
    constant stCalc : STD_LOGIC := '1';

    signal bitCnt : INTEGER range 0 to 7; -- counts bit in stCalc
    signal byteCnt : INTEGER range 0 to 4; -- counts the four initial bytes
    signal crcValueInt : STD_LOGIC_VECTOR (31 downto 0); -- stores current
    crc
    signal latchedByte : STD_LOGIC_VECTOR (7 downto 0); -- latches input
    byte
    signal reversedByte : STD_LOGIC_VECTOR (7 downto 0); -- bit
    reversedinByte
    signal lastNewByte : STD_LOGIC; -- previous value of newByte




    -- Generator polynomial is
    -- 32 26 23 22 16 12 11 10 8 7 5 4 2
    -- x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1
    constant GENERATOR : STD_LOGIC_VECTOR := X"04C11DB7";




    begin

    ------------------------------------------------------------------------------------
    process(crcValueInt)
    -- Output is the inverted bit reversal of the internal signal
    begin
    for i in 0 to 31 loop -- invert and bit reverse
    crcValue(i) <= NOT crcValueInt(31-i);
    end loop;
    end process;


    -------------------------------------------------------------------------------------


    process (inByte)
    -- Bit reversed version of inByte
    begin
    for i in 0 to 7 loop -- bit reverse
    reversedByte(i) <= inByte(7 - i);
    end loop;
    end process;


    --------------------------------------------------------------------------------------



    process (clk,rst)
    -- FSM
    begin
    if rst = '0' then -- reset signals to starting values
    presState <= stIdle;
    bitCnt <= 0;
    byteCnt<= 0;
    crcValueInt <= (others => '0');
    lastNewByte <= '0';
    elsif clk'event and clk = '1' then -- operate on positive edge
    lastNewByte <= newByte; -- remember previous value
    case presState is
    when stIdle =>
    bitCnt <= 0;
    crcValid <= '1';
    if newFrame = '1' then -- reset crcGenerator to starting values
    presState <= stIdle;
    byteCnt <= 0;
    crcValueInt <= (others => '0');
    crcValid <= '0';
    elsif newByte = '1' and lastNewByte = '0' then -- positive edge
    if byteCnt /= 4 then -- shift in inverted byte
    presState <= stIdle;
    crcValueInt <= crcValueInt(23 downto 0) & NOT reversedByte;
    byteCnt <= byteCnt + 1;
    crcValid <= '0';
    else -- go to calculation state after fourth byte
    presState <= stCalc;
    latchedByte <= inByte; -- latch inByte
    crcValid <= '0';
    end if;
    end if;
    when stCalc => -- shift in byte in little-endian and XOR if
    necessary
    crcValid <= '0';
    if newFrame = '1' then -- reset crcGenerator to starting values
    presState <= stIdle;
    crcValueInt <= (others => '0');
    crcValid <= '0';
    bitCnt <= 0;
    else -- shift in current bit, LSB first.
    if crcValueInt(31) = '1' then -- XOR with generator if MSB is '1'
    crcValueInt <= (crcValueInt(30 downto 0) & latchedByte(bitCnt))
    XOR GENERATOR;
    else
    crcValueInt <= (crcValueInt(30 downto 0) & latchedByte(bitCnt));
    end if;
    if bitCnt = 7 then -- stop after all bits are shifted in
    presState <= stIdle;
    crcValid <= '1';
    bitCnt <= 0;
    else -- move to next bit
    presState <= stCalc;
    crcValid <= '0';
    bitCnt <= bitCnt + 1;
    end if;
    end if;
    when others =>
    presState <= stIdle;
    crcValid <= '0';
    bitCnt <= 0;
    end case;
    end if;
    end process;
    end crcGenerator_arch;









    THE testbench code is
    library IEEE;
    use IEEE.std_logic_1164.all;
    USE IEEE.std_logic_signed.ALL;
    USE IEEE.std_logic_arith.ALL;
    use STD.textio.all;

    entity tb_CRC is

    generic (WIDTH_BYTE : integer:=8;
    WIDTH_CRC : integer:=32
    );

    end tb_CRC;




    architecture Structural of tb_CRC is


    ------ Component Under Test Declaration ----------------


    component crcGenerator

    generic (WIDTH_BYTE : integer:=8;
    WIDTH_CRC : integer:=32
    );
    port (
    clk : in STD_LOGIC; -- Input clock
    rst : in STD_LOGIC; --
    Asynchronous active low reset
    newFrame : in STD_LOGIC; --
    Assert to restart calculations
    newByte : in STD_LOGIC; --
    Assert to indicate a crcValid input byte
    inByte : in STD_LOGIC_VECTOR (WIDTH_BYTE-1 downto 0); --
    Input byte
    crcValid : out STD_LOGIC; -- Indicates
    crcValid CRC. Active HIGH
    crcValue : out STD_LOGIC_VECTOR (WIDTH_CRC-1 downto 0) --
    CRC output
    );

    end component;


    -----------------------------------------------------------------
    -----------------------------------------------------------------
    signal S_clk : STD_LOGIC := '0';
    signal S_rst : STD_LOGIC := '1';
    signal S_newFrame : STD_LOGIC := '0';
    signal S_newByte : STD_LOGIC := '0';
    signal S_inByte : STD_LOGIC_VECTOR (7 downto 0);
    signal S_crcValid : STD_LOGIC:='0';
    signal S_crcValue : STD_LOGIC_VECTOR (31 downto 0);
    signal S_count : integer := 0;



    begin


    S_clk<= not S_clk after 10 ns;
    S_rst<= '0' after 20 ns;



    process(S_clk,S_rst)
    begin
    if S_rst='0' then
    if S_clk'event and S_clk = '1' then
    S_count <= S_count+1 ;
    end if;
    end if;


    end process;


    process(S_count)
    begin

    case S_count is
    when 0 =>
    if S_clk'event and S_clk = '1' then
    S_inByte<=x"00";
    end if;
    when 1 =>
    if S_clk'event and S_clk = '1' then
    S_inByte<=x"00";
    end if;
    when 2 =>
    if S_clk'event and S_clk = '1' then
    S_newFrame<='1';
    end if;
    when 3 =>
    if S_clk'event and S_clk = '1' then
    S_newFrame<='0';
    end if;
    when 4 =>
    if S_clk'event and S_clk = '1' then
    S_newByte<='1';
    S_inByte<=x"DD";
    else
    S_newByte<='0';
    end if;
    when 5 =>
    if S_clk'event and S_clk = '1' then
    S_newByte<='1';
    S_inByte<=x"EE";
    else
    S_newByte<='0';
    end if;

    when others =>
    if S_clk'event and S_clk = '1' then
    S_newByte<='1';
    S_inByte<=x"00";
    else
    S_newByte<='0';
    end if;

    end case;


    end process;


    DUT: crcGenerator

    generic map ( WIDTH_BYTE => 8,
    WIDTH_CRC => 32
    )

    port map (
    clk => S_clk,
    rst => S_rst,
    newFrame => S_newFrame,
    newByte => S_newByte,
    inByte => S_inByte,
    crcValid => S_crcValid,
    crcValue => S_crcValue
    );

    END Structural;
    crazyrdx, Feb 15, 2006
    #1
    1. Advertising

  2. crazyrdx

    Ajeetha Guest

    Hi,
    Didn't test it through, but for sure you don't need the "if
    S_clk'event " stuff in your second process:

    i.e.

    process(S_count)
    begin

    case S_count is
    when 0 =>
    >>>> if S_clk'event and S_clk = '1' then
    >>> Remove this...

    S_inByte<=x"00";
    end if;
    when 1 =>

    HTH
    Ajeetha, CVC
    www.noveldv.com
    Ajeetha, Feb 15, 2006
    #2
    1. Advertising

  3. crazyrdx

    crazyrdx Guest

    Thanks, still checking it out

    Rishi
    crazyrdx, Feb 18, 2006
    #3
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. rajan
    Replies:
    1
    Views:
    2,737
    Marcin
    Jul 29, 2003
  2. Replies:
    10
    Views:
    2,600
    Simon Peacock
    Oct 1, 2005
  3. Guido
    Replies:
    3
    Views:
    3,215
    Mike Treseler
    Jan 30, 2006
  4. Nemesis
    Replies:
    5
    Views:
    1,324
    Nemesis
    Mar 13, 2007
  5. Olaf
    Replies:
    1
    Views:
    1,973
    Mike Treseler
    Sep 25, 2007
Loading...

Share This Page