Problem with TextIO

Discussion in 'VHDL' started by Rob Keiber, Jul 7, 2008.

  1. Rob Keiber

    Rob Keiber Guest

    Hi

    I get the following error with the code fragment beneath, can anybody
    tell me what is wrong?

    Error: Subprogram write is "ambigious"
    Error: Type error resolving function call: write.

    library IEEE;
    use IEEE.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use std.textio.all;
    ....

    process(clk)
    variable s : line;
    begin
    ...
    write(s,"Test 1 - ");
    write(s,"\n");
    writeline(output,s);
    ...

    Many thanks,
    Rob
     
    Rob Keiber, Jul 7, 2008
    #1
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  2. Rob Keiber a écrit :
    > Hi
    >
    > I get the following error with the code fragment beneath, can anybody
    > tell me what is wrong?
    >
    > Error: Subprogram write is "ambigious"
    > Error: Type error resolving function call: write.
    >
    > library IEEE;
    > use IEEE.std_logic_1164.all;
    > use ieee.std_logic_unsigned.all;
    > use std.textio.all;
    > ....
    >
    > process(clk)
    > variable s : line;
    > begin
    > ...
    > write(s,"Test 1 - ");
    > write(s,"\n");
    > writeline(output,s);
    > ...



    For some reason (if somebody could explain, it is still unclear to me)
    it is not clear what type your litteral constants are.
    Try :
    write (s, string'("Test 1 - "));

    Nicolas
     
    Nicolas Matringe, Jul 7, 2008
    #2
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  3. Rob Keiber

    Rob Keiber Guest

    > For some reason (if somebody could explain, it is still unclear to me)
    > it is not clear what type your litteral constants are.
    > Try :
    > write (s, string'("Test 1 - "));


    > Nicolas


    Thanks Nicolas it works now for the compiling. However, the line

    writeline(output,s);

    doesnt output anything on the ModelSim Console. is this probably not
    working with Modelsim 5.7d or is there another issue?

    Cheers,
    Rob
     
    Rob Keiber, Jul 7, 2008
    #3
  4. On 7 Jul., 20:46, Rob Keiber <> wrote:
    > I get the following error with the code fragment beneath, can anybody
    > tell me what is wrong?


    > write(s,"Test 1 - ");


    You need to qualify the string to distinguish between string and
    vector.

    write(s, string'("Test 1 - "));

    BTW the writeline command inserts a CR at line end. I don't think VHLD
    supports "\n".

    regards Thomas
     
    Thomas Stanka, Jul 8, 2008
    #4
  5. Rob Keiber

    Alain Guest

    Hello,

    Try :

    ....
    write(s,string'("Test 1 - "));
    write(s,string'("\n"));
    ....

    Regards
     
    Alain, Jul 8, 2008
    #5
  6. Rob Keiber

    Guest

    Are you sure that your process ever gets to the lines

    write(s,"Test 1 - ");
    write(s,"\n");
    writeline(output,s);

    ?

    Maybe some "wait until" condition before is not satisfied.

    Use some test signal to proof that ...

    Rgds
    Andre
     
    , Jul 8, 2008
    #6
  7. Rob Keiber

    Tricky Guest


    > For some reason (if somebody could explain, it is still unclear to me)
    > it is not clear what type your litteral constants are.
    > Try :
    >    write (s, string'("Test 1 - "));
    >
    > Nicolas


    Basically, the string could be either a bit_vector or a string, and
    the compile doesnt know which it is as it does not (and cannot)
    evaluate the contents of the string.

    > doesnt output anything on the ModelSim Console. is this probably not
    > working with Modelsim 5.7d or is there another issue?


    In 6.1g (and I assume older versions): When you start a simulation in
    modelsim, it gives you the option to write to a file instead of the
    console. (Under TEXTIO files, STD_INPUT and STD_OUTPUT). Make sure you
    havent set these to something (and hence writing into/out them).

    Also, I notice you've got: write(s,"\n");
    This does not add a newline character, but is the literals '\' and
    'n'. to write a newline character you need to use: write(s, LF); But
    the writeline() function already does that for you, so in effect you'd
    just be adding an extra blank line.
    There is no escape character in VHDL like in C, which makes putting
    the " character into a string a pain (please someone correct me if Im
    wrong).
     
    Tricky, Jul 8, 2008
    #7
  8. Tricky <> writes:

    > There is no escape character in VHDL like in C, which makes putting
    > the " character into a string a pain (please someone correct me if Im
    > wrong).


    Just put double-double quotes in:

    report "Look, a "" in my message";

    I can't remember where learned that nugget from (but I bet not from
    reading the LRM :)

    Cheers,
    Martin

    --

    TRW Conekt - Consultancy in Engineering, Knowledge and Technology
    http://www.conekt.net/electronics.html
     
    Martin Thompson, Jul 10, 2008
    #8
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