Problem with use of real type in VHDL

Discussion in 'VHDL' started by vahid_6485, Apr 10, 2008.

  1. vahid_6485

    vahid_6485

    Joined:
    Apr 10, 2008
    Messages:
    1
    Hi all
    I am using quartusII version4 for compiling and simulating VHDL codes.
    I have a problem with use of real type in VHDL, i am using mathpack and write:
    (download from http://www.csee.umbc.edu/help/VHDL/stdpkg.html)

    library IEEE;
    use IEEE.math_real.all;

    but i has a lot of error when compiling such as
    Error: VHDL package error at mathpack.vhd(45): package math_real already exists
    Error: VHDL Use Clause error at mathpack.vhd(1175): design library ieee does not contain primary unit math_real
    Error: VHDL error at mathpack.vhd(1187): object real is used but not declared

    Kind regards for your help
    _________________
    Vahid
    vahid_6485, Apr 10, 2008
    #1
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