problems with 4 to 1 multiplexer

Discussion in 'VHDL' started by Lily, Apr 23, 2004.

  1. Lily

    Lily Guest

    Hi,

    i need help with this 4 to 1 multiplexer. Here is my part of my program

    --declaration for signals & constants
    signal mux_out_arith,mux_out_logic : std_logic_vector(3 downto 0);
    signal op_add, op_inc, op_sub, op_cmp, op_and : std_logic_vector(3 downto 0);

    constant add : std_logic_vector(3 downto 0):="0000";
    constant inc : std_logic_vector(3 downto 0):="0001";
    constant sub : std_logic_vector(3 downto 0):="0010";
    constant cmp : std_logic_vector(3 downto 0):="0011";

    arith_mux4_1 : process (op_add,op_inc,op_sub,op_cmp, sel)
    begin
    case sel is
    when "0000" => mux_out_arith <= op_add;
    when "0001" => mux_out_arith <= op_sub;
    when "0011" => mux_out_arith <= op_inc;
    when others => mux_out_arith <= op_cmp;
    end case;
    end process arith_mux4_1;

    when i compile i've got error something like this
    Type error in string literal (base type is not ARRAY_TYPE).
    can anybody out there help me ?

    thanks.
     
    Lily, Apr 23, 2004
    #1
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  2. Lily

    Jon Parker Guest

    Hi Lily,

    It might be that you forgot to include a library declaration at the
    top of your file. The error message sounds like it is interpreting
    your std_logic_vectors "0000", etc. as strings instead of vectors.

    Best regards,
    Jon Parker


    (Lily) wrote in message news:<>...
    > Hi,
    >
    > i need help with this 4 to 1 multiplexer. Here is my part of my program
    >
    > --declaration for signals & constants
    > signal mux_out_arith,mux_out_logic : std_logic_vector(3 downto 0);
    > signal op_add, op_inc, op_sub, op_cmp, op_and : std_logic_vector(3 downto 0);
    >
    > constant add : std_logic_vector(3 downto 0):="0000";
    > constant inc : std_logic_vector(3 downto 0):="0001";
    > constant sub : std_logic_vector(3 downto 0):="0010";
    > constant cmp : std_logic_vector(3 downto 0):="0011";
    >
    > arith_mux4_1 : process (op_add,op_inc,op_sub,op_cmp, sel)
    > begin
    > case sel is
    > when "0000" => mux_out_arith <= op_add;
    > when "0001" => mux_out_arith <= op_sub;
    > when "0011" => mux_out_arith <= op_inc;
    > when others => mux_out_arith <= op_cmp;
    > end case;
    > end process arith_mux4_1;
    >
    > when i compile i've got error something like this
    > Type error in string literal (base type is not ARRAY_TYPE).
    > can anybody out there help me ?
    >
    > thanks.
     
    Jon Parker, Apr 23, 2004
    #2
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  3. Lily

    Lily Guest

    Hi Jon,

    the libraries that i have declared on top of my program are:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    is that enough or i have missed any library declaration ?

    thanks a lot,
    lily.

    (Jon Parker) wrote in message news:<>...
    > Hi Lily,
    >
    > It might be that you forgot to include a library declaration at the
    > top of your file. The error message sounds like it is interpreting
    > your std_logic_vectors "0000", etc. as strings instead of vectors.
    >
    > Best regards,
    > Jon Parker
    >
    >
    > (Lily) wrote in message news:<>...
    > > Hi,
    > >
    > > i need help with this 4 to 1 multiplexer. Here is my part of my program
    > >
    > > --declaration for signals & constants
    > > signal mux_out_arith,mux_out_logic : std_logic_vector(3 downto 0);
    > > signal op_add, op_inc, op_sub, op_cmp, op_and : std_logic_vector(3 downto 0);
    > >
    > > constant add : std_logic_vector(3 downto 0):="0000";
    > > constant inc : std_logic_vector(3 downto 0):="0001";
    > > constant sub : std_logic_vector(3 downto 0):="0010";
    > > constant cmp : std_logic_vector(3 downto 0):="0011";
    > >
    > > arith_mux4_1 : process (op_add,op_inc,op_sub,op_cmp, sel)
    > > begin
    > > case sel is
    > > when "0000" => mux_out_arith <= op_add;
    > > when "0001" => mux_out_arith <= op_sub;
    > > when "0011" => mux_out_arith <= op_inc;
    > > when others => mux_out_arith <= op_cmp;
    > > end case;
    > > end process arith_mux4_1;
    > >
    > > when i compile i've got error something like this
    > > Type error in string literal (base type is not ARRAY_TYPE).
    > > can anybody out there help me ?
    > >
    > > thanks.
     
    Lily, Apr 23, 2004
    #3
  4. Lily

    ivero Guest

    What type do you declared sel signal? Maybe you declared as std_logic_vector
    (1 downto 0).

    > case sel is
    > when "0000" => mux_out_arith <= op_add;
    > when "0001" => mux_out_arith <= op_sub;
    > when "0011" => mux_out_arith <= op_inc;
    > when others => mux_out_arith <= op_cmp;
    > end case;
     
    ivero, Apr 23, 2004
    #4
  5. Lily

    Lily Guest

    Re: problems with 4 to 1 multiplexer -> solved :) how to assign 4 bits signal ?

    thanks ivero. it solved my problem !!! :)
    i didnt realise that i actually declared the sel signal as std_logic
    instead of std_logic_vector (3 downto 0).
    btw one more question since my sel signal consist of 4 bits, and i'd
    like to assign each one of the bit to my multiplexers (say when my sel
    signal is 0001 first multiplexer is high, 0010 second multiplexer is
    high and 0100 the third multiplexer is high. currently i have 3
    processes for each multiplexer. how do i implement this in vhdl ?

    thanks a lot.


    "ivero" <> wrote in message news:<yTeic.117405$>...
    > What type do you declared sel signal? Maybe you declared as std_logic_vector
    > (1 downto 0).
    >
    > > case sel is
    > > when "0000" => mux_out_arith <= op_add;
    > > when "0001" => mux_out_arith <= op_sub;
    > > when "0011" => mux_out_arith <= op_inc;
    > > when others => mux_out_arith <= op_cmp;
    > > end case;
     
    Lily, Apr 24, 2004
    #5
  6. Lily

    ivero Guest

    Re: problems with 4 to 1 multiplexer -> solved :) how to assign 4 bits signal ?


    > btw one more question since my sel signal consist of 4 bits, and i'd
    > like to assign each one of the bit to my multiplexers (say when my sel
    > signal is 0001 first multiplexer is high, 0010 second multiplexer is
    > high and 0100 the third multiplexer is high. currently i have 3
    > processes for each multiplexer. how do i implement this in vhdl ?


    I think i don't understand the ploblem (my english is not very good), maybe
    what you mean is something like:

    case sel is
    when "0001" => mux_out_arith <= op_add;
    when "0010" => mux_out_arith <= op_sub;
    when "0100" => mux_out_arith <= op_inc;
    when "1000" => mux_out_arith <= op_cmp;
    when others => null;
    end case;

    Good bye.
     
    ivero, Apr 24, 2004
    #6
  7. Lily

    Eric Smith Guest

    Re: problems with 4 to 1 multiplexer -> solved :) how to assign 4 bits signal ?

    "ivero" <> writes:
    > I think i don't understand the ploblem (my english is not very good), maybe
    > what you mean is something like:
    >
    > case sel is
    > when "0001" => mux_out_arith <= op_add;
    > when "0010" => mux_out_arith <= op_sub;
    > when "0100" => mux_out_arith <= op_inc;
    > when "1000" => mux_out_arith <= op_cmp;
    > when others => null;
    > end case;


    You do NOT want a "others => null" in a multiplexer, as the synthesizer
    will have to infer a latch, because you're saying that mux_out_arith
    should not change value when sel is not one of the four explicitly
    specified choices. It would be much better to put an explicit
    assignment in the others clause, which could assign a constant value or
    or the same value as one of the other cases.
     
    Eric Smith, Apr 29, 2004
    #7
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