problems with behavioral compiler

Discussion in 'VHDL' started by YiYin Wang, Sep 27, 2004.

  1. YiYin Wang

    YiYin Wang Guest

    Dear All,
    I have used the Behavioral Compiler to synthesize a FIR filter.
    I want to constrain a loop. But when I use " find " command to find the
    loop, it always reports error and get no results.

    the command I used is
    "bc_shell> find cell -hierarchy *filter_loop*"
    and the feedback is :
    "Error: Can't find object '*filter_loop*'.(UID-109)
    {}"

    How could I solve this problem?

    Thanks a lot.
    Best Regards

    Yiyin Wang
    My code is below:

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_arith.ALL;
    USE ieee.std_logic_signed.ALL;

    ENTITY fir_filter2 IS
    PORT (
    clk : IN std_logic;
    rst : IN std_logic;
    load : IN std_logic;
    data_in : IN signed( 11 DOWNTO 0 );
    coeff_addr : IN unsigned( 3 DOWNTO 0 );
    start : IN std_logic;
    data_out : OUT signed( 11 DOWNTO 0 )
    );
    END fir_filter2;

    ARCHITECTURE behavioral OF fir_filter2 IS
    BEGIN

    main_proc: PROCESS

    SUBTYPE coeff_element IS signed( 11 DOWNTO 0 );
    TYPE coeff_type IS ARRAY ( integer RANGE <> ) OF
    coeff_element;
    VARIABLE coeff : coeff_type( 0 TO 14 );

    SUBTYPE history_element IS signed( 11 DOWNTO 0 );
    TYPE history_type IS ARRAY ( integer RANGE <> ) OF
    history_element;
    VARIABLE history : history_type( 0 TO 14 );

    VARIABLE sum : signed( 23 DOWNTO 0 );
    ATTRIBUTE unroll_new_instance : boolean;
    ATTRIBUTE unroll_new_instance OF sum : VARIABLE IS true;

    BEGIN

    reset_loop: LOOP

    --
    -- reset the data output
    --

    data_out <= ( OTHERS => '0' );

    WAIT UNTIL clk'EVENT AND ( clk = '1' );
    EXIT reset_loop WHEN ( rst = '1' );


    --
    -- Initialize all coefficients to zero
    --
    FOR i IN 0 TO 14 LOOP
    coeff( i ) := ( OTHERS => '0' );
    END LOOP;

    --
    -- Initialize history memory to zero
    --
    FOR i IN 0 TO 14 LOOP
    history( i ) := ( OTHERS => '0' );
    END LOOP;

    main_loop: LOOP

    config_loop: LOOP

    --
    -- Wait until next clock cycle to check for
    -- load or filter signals.
    --
    WAIT UNTIL clk'EVENT AND ( clk = '1' );
    EXIT reset_loop WHEN ( rst = '1' );

    IF ( start = '1' ) THEN
    EXIT config_loop;
    END IF;

    IF ( load = '1' ) THEN
    coeff( conv_integer( '0' & coeff_addr ) ) :=
    data_in;
    END IF;

    END LOOP config_loop;

    --
    -- Main filter loop
    --
    filter_loop: LOOP -- pragma n_unroll 3
    -- pragma pipeline_init_interval 1

    WAIT UNTIL clk'EVENT AND ( clk = '1' );
    EXIT reset_loop WHEN ( rst = '1' );

    history( 0 ) := signed( data_in );

    sum := ( ( ( history( 0 ) * coeff( 0 ) +
    history( 1 ) * coeff( 1 ) ) +
    ( history( 2 ) * coeff( 2 ) +
    history( 3 ) * coeff( 3 ) ) ) +
    ( ( history( 4 ) * coeff( 4 ) +
    history( 5 ) * coeff( 5 ) ) +
    ( history( 6 ) * coeff( 6 ) +
    history( 7 ) * coeff( 7 ) ) ) ) +
    ( ( ( history( 8 ) * coeff( 8 ) +
    history( 9 ) * coeff( 9 ) ) +
    ( history( 10 ) * coeff( 10 ) +
    history( 11 ) * coeff( 11 ) ) ) +
    ( ( history( 12 ) * coeff( 12 ) +
    history( 13 ) * coeff( 13 ) ) +
    history( 14 ) * coeff( 14 ) ) );

    data_out <= sum( 23 DOWNTO 12 );

    FOR i IN 14 DOWNTO 1 LOOP
    history( i ) := history( i - 1 );
    END LOOP;

    END LOOP filter_loop;

    END LOOP main_loop;

    END LOOP reset_loop;

    END PROCESS;

    END behavioral;
     
    YiYin Wang, Sep 27, 2004
    #1
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  2. Did this process simulate as you expected?
    Consider recoding this in a single synchronous
    process without all the loops.

    -- Mike Treseler
     
    mike_treseler, Sep 27, 2004
    #2
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