problems with generate statement

Discussion in 'VHDL' started by eengineer101@gmail.com, Jun 20, 2006.

  1. Guest

    I am generating a 39 bit adder which takes an input from a multiplier
    in ise 7.1. The problem is that when the inputs (the summands) are
    defined as signals, XST will completely omit the adder from the design
    and gives warnings. If the inputs are taken directly from pins in the
    entity declaration, the adder synthesizes correctly.

    Relevant code:

    entity testAdd is
    GENERIC ( n : INTEGER := 39 ) ;
    port (

    IN1,IN2 : in std_logic_vector(38 downto 0);
    S : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
    );
    end entity testAdd;

    architecture behv of testAdd is
    SIGNAL s1,s2 : STD_LOGIC_VECTOR (38 downto 0);
    SIGNAL C : STD_LOGIC_VECTOR(0 TO n) ;
    begin

    ....
    ....
    ....
    C(0) <= '0' ;
    Generate_label:
    FOR i IN 0 TO n-1 GENERATE
    --stage: fulladd PORT MAP ( C(i), s1(i), s2(i), S(i), C(i+1) );
    --doesn't work
    stage: fulladd PORT MAP ( C(i),
    IN1(i), IN2(i), S(i), C(i+1) ); --works
    END GENERATE ;
    ....
    ....
    ....
    end architecture behv;


    Low Level Synthesis *
    =========================================================================
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage11/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage10/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage9/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance is
    removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage8/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance is
    removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage7/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance is
    removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage6/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance is
    removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage38/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage37/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage0/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance is
    removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage1/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance is
    removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage2/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance is
    removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage3/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance is
    removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage4/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance is
    removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage5/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance is
    removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage36/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage35/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage34/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage33/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage32/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage31/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage30/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage29/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage28/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage27/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage26/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage25/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage24/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage23/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage22/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage21/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage20/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage19/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage18/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage17/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage16/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage15/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage14/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed
    WARNING:Xst:1989 - Unit <testadd>: instances <stage12/Mxor_s>,
    <stage13/Mxor_s> of unit <LPM_XOR3_1> are equivalent, second instance
    is removed


    Does anybody understand why this happens?

    Thanks!


    sarah
     
    , Jun 20, 2006
    #1
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  2. hi firend,
    Assign the inputs to the signal then try to generate.
    s1<= IN1;
    s2<= IN2;

    i dont know will it work or not.
    but try this. i dont have VHDL simulator otherwise i would have tried
    it.
     
    dipesh.trivedi, Jun 20, 2006
    #2
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  3. Rtafas Guest

    Agreed. It probably would work.

    dipesh.trivedi escreveu:

    > hi firend,
    > Assign the inputs to the signal then try to generate.
    > s1<= IN1;
    > s2<= IN2;
    >
    > i dont know will it work or not.
    > but try this. i dont have VHDL simulator otherwise i would have tried
    > it.
     
    Rtafas, Jun 20, 2006
    #3
  4. Guest

    Thanks for your reply. Actually, the inputs pass through a multiplier
    stage prior to entering the adder. Connecting the inputs to
    intermediary signals will work, as you suggest, but it doesn't fit the
    design.

    sarah

    dipesh.trivedi wrote:
    > hi firend,
    > Assign the inputs to the signal then try to generate.
    > s1<= IN1;
    > s2<= IN2;
    >
    > i dont know will it work or not.
    > but try this. i dont have VHDL simulator otherwise i would have tried
    > it.
     
    , Jun 20, 2006
    #4
  5. wrote:

    > I am generating a 39 bit adder which takes an input from a multiplier
    > in ise 7.1.


    library IEEE;
    use IEEE.Numeric_std.ALL;

    signal A,B,result : std_ulogic_vector(38 downto 0);

    result<=std_ulogic_vector( unsigned(A) + unsigned(B) );

    That's all. It synthesizes to a CRA if you don't set speed constraints
    and to a faster adder (e.g. CLA) if your speed constraints are harder.
    Why do you need such a bunch of code?


    > The problem is that when the inputs (the summands) are
    > defined as signals, XST will completely omit the adder from the design
    > and gives warnings. If the inputs are taken directly from pins in the
    > entity declaration, the adder synthesizes correctly.


    So you have written something that makes the synthesis tool think, that
    this adder is not needed.


    > entity testAdd is
    > GENERIC ( n : INTEGER := 39 ) ;
    > port (
    >
    > IN1,IN2 : in std_logic_vector(38 downto 0);
    > S : OUT STD_LOGIC_VECTOR(n-1 DOWNTO 0)
    > );
    > end entity testAdd;


    I am just curious: Why do you need such an adder inside a component
    which furthermore is manually build by instances of fulladders?

    IN1 and IN2 should also depend on the generic n to be flexible.


    > architecture behv of testAdd is
    > SIGNAL s1,s2 : STD_LOGIC_VECTOR (38 downto 0);


    Why do you need extra signals s1, s2? What is the purpose of them? Do
    they hold the input summands? Why don't you just read IN1 and IN2 if I
    guess right?


    > SIGNAL C : STD_LOGIC_VECTOR(0 TO n) ;


    Why not downto? It often makes designs harder to read if you use
    different directions.


    > C(0) <= '0' ;
    > Generate_label:
    > FOR i IN 0 TO n-1 GENERATE
    > --stage: fulladd PORT MAP ( C(i), s1(i), s2(i), S(i), C(i+1) );
    > --doesn't work
    > stage: fulladd PORT MAP ( C(i),
    > IN1(i), IN2(i), S(i), C(i+1) ); --works
    > END GENERATE ;


    If you read s1 and s2 but never write to them, it is obvious, that the
    synthesis tool is smart enough to optimize these useless signals away.


    Ralf
     
    Ralf Hildebrandt, Jun 20, 2006
    #5
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