Problems with GHDL and GTKWave

Discussion in 'VHDL' started by Christian Christmann, Nov 15, 2006.

  1. Hi,

    I'm new to VHDL. After looking for a free VHDL simulator
    I found GHDL.

    I started reading the manual and wanted to implement a
    full adder as described here:
    http://ghdl.free.fr/ghdl/A-full-adder.html#A-full-adder

    So, first of all I've implemented the full adder with a
    behavioral description:
    ------
    entity adder is
    port( i0, i1 : in bit;
    ci : in bit;
    s : out bit;
    co : out bit );
    end adder;

    architecture rtl of adder is
    begin
    s <= i0 xor i1 xor ci;
    co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
    end rtl;
    -------

    and analyzed it with "ghdl -a adder.vhdl".

    Then I wrote the testbench adder_tb.vhdl:

    ----------
    entity adder_tb is
    end adder_tb;

    architecture behav of adder_tb is
    component adder
    port ( i0, i1 : in bit;
    ci : in bit;
    s : out bit;
    co : out bit );
    end component;

    for adder_0: adder use entity work.adder;
    signal i0, i1, ci, s, co : bit;
    begin
    adder_0: adder port map( i0 => i0, i1 => i1, ci => ci,
    s => s, co => co );

    process
    type pattern_type is record
    i0, i1, ci : bit;
    s, co : bit;
    end record;

    type pattern_array is array (natural range <>) of pattern_type;
    constant patterns : pattern_array :=
    (('0', '0', '0', '0', '0'),
    ('0', '0', '1', '1', '0'),
    ('0', '1', '0', '1', '0'),
    ('0', '1', '1', '0', '1'),
    ('1', '0', '0', '1', '0'),
    ('1', '0', '1', '0', '1'),
    ('1', '1', '0', '0', '1'),
    ('1', '1', '1', '1', '1'));

    begin
    for i in patterns'range loop
    i0 <= patterns(i).i0;
    i1 <= patterns(i).i1;
    ci <= patterns(i).ci;

    wait for 1 ns;

    assert s = patterns(i).s
    report "bad sum value" severity error;
    assert co = patterns(i).co
    report "bad carray out value" severity error;

    end loop;
    assert false report "end of test" severity note;
    wait;
    end process;
    end behav;
    -----------

    After analyzing with "ghdl -a adder_tb.vhdl", building
    with "ghdl -e adder_tb" and finally running the testbench
    with "ghdl -r adder_tb --vcd=adder.vcd", I get the VCD
    waveform adder.vcd.

    Then I wanted to view the waveform output with gtkwave,
    but after "gtkwave adder.vcd" I don't see the waves but an
    empty window. Any ideas what's wrong?
    Or do I have to set up gtkwave?

    Thank you.

    Chris
     
    Christian Christmann, Nov 15, 2006
    #1
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  2. Christian Christmann

    Guest

    Christian Christmann wrote:

    > Then I wanted to view the waveform output with gtkwave,
    > but after "gtkwave adder.vcd" I don't see the waves but an
    > empty window. Any ideas what's wrong?
    > Or do I have to set up gtkwave?


    You have to import the traces from the tree or hierarchy requesters.
    As a trace could have thousands of nets, they're not imported
    automatically.

    Turn to page 44 (Displaying Waveforms) in the User's Guide which can be
    found on a link at the bottom of http://home.nc.rr.com/gtkwave/

    -t
     
    , Nov 15, 2006
    #2
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