problems with inout port

Discussion in 'VHDL' started by Cazed, Feb 2, 2006.

  1. Cazed

    Cazed Guest

    Hi,

    I'm trying to interface my fpga with a 8051-uC using the external memory
    feature. My problem is that according to my simulations the bus does not
    output anything back to aLow (aLow multiplexes low eight address bits and
    bidirectional data) when I try to read...Writing data seems to be working
    fine though...

    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;



    entity interface is
    port(
    aHigh : in std_logic; --Address MSB only one bit needed
    aLow : inout std_logic_vector(7 downto 0); --Address LSB
    ALE : in std_logic; --adress latch
    WE : in std_logic; --Write enable
    RD : in std_logic; --Read data
    --Internal registers
    RAMctrl : buffer std_logic_vector(1 downto 0);
    RAMaddress : buffer std_logic_vector(5 downto 0);
    RAMdata : buffer std_logic_vector(12 downto 0));
    end interface;


    architecture behave of interface is
    signal address : std_logic_vector(8 downto 0);
    begin
    --latch in address
    process(aHigh, aLow, ALE)
    begin
    if falling_edge(ALE) then --Latch in address
    address(8) <= aHigh;
    address(7 downto 0) <= aLow;
    end if;
    end process;

    process(address, WE)
    begin
    if rising_edge(WE) then --write to register
    case address is
    when "100000000" => NULL; --STATUS
    when "110000001" => RAMdata(7 downto 0) <= aLow;
    --CRDLSB
    when "110000010" => RAMdata(12 downto 8) <=aLow(4 downto
    0);--CRDMSB
    when "110000011" => RAMaddress <= aLow(5 downto 0);
    --CRADDRESS
    when "110000000" => RAMctrl <= aLow(1 downto 0);
    --CRCONTROL
    when OTHERS => NULL;
    end case;
    end if;
    end process;

    process(address, RD)
    begin
    if falling_edge(RD) then
    case address is
    when "100000000" => NULL; --STATUS
    when "110000001" => aLow <= RAMdata(7 downto 0);
    --CRDLSB
    when "110000010" => aLow(4 downto 0) <= RAMdata(12 downto
    8);--CRDMSB
    when "110000011" => aLow(5 downto 0) <= RAMaddress;
    when "110000000" => aLow(1 downto 0) <= RAMctrl;
    when OTHERS => NULL;
    end case;
    end if;
    if rising_edge(RD) then
    aLow <= "ZZZZZZZZ";
    end if;
    end process;
    end behave;

    Does the simulated input be anything special to allow the readprocess to
    output data on aLow?

    Regards
    /Åke "Cazed" Forslund
     
    Cazed, Feb 2, 2006
    #1
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  2. Cazed wrote:

    > I'm trying to interface my fpga with a 8051-uC using the external memory
    > feature. My problem is that according to my simulations the bus does not
    > output anything back to aLow (aLow multiplexes low eight address bits and
    > bidirectional data) when I try to read...Writing data seems to be working
    > fine though.


    Consider adding a clock input and
    synchronizing your processes, or better
    yet, do it all in one process.

    -- Mike Treseler
     
    Mike Treseler, Feb 2, 2006
    #2
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  3. Dear Åke Forslund,

    One possible problem with the code is that you had

    process(address, WE)
    begin
    if rising_edge(WE) then --write to register
    case address is
    when "100000000" => NULL; --STATUS
    when "110000001" => RAMdata(7 downto 0) <= aLow;
    --CRDLSB
    when "110000010" => RAMdata(12 downto 8) <=aLow(4 downto
    0);--CRDMSB
    when "110000011" => RAMaddress <= aLow(5 downto 0);
    --CRADDRESS
    when "110000000" => RAMctrl <= aLow(1 downto 0);
    --CRCONTROL
    when OTHERS => NULL;
    end case;
    end if;
    end process;

    in which you mentioned only address, WE in the sensitivity list but
    possibly performed assignments with aLow so I suggest putting aLow into
    the sensitivity list too.

    Similarly for the reading process, I suggest
    address, RD, RAMdata, RAMaddress, RAMctrl
    for the sensitivity list.

    Overall your code looks nice, but I fear that I have not solved the
    problem you reported.

    I hope you manage to get it working.

    Regards,
    Colin Paul Gloster
     
    Colin Paul Gloster, Feb 3, 2006
    #3
  4. Cazed

    jens Guest

    > in which you mentioned only address, WE in the sensitivity list but
    > possibly performed assignments with aLow so I suggest putting aLow into
    > the sensitivity list too.


    For an edge-triggered process without any asynchronous controls, the
    clock (or WE in this case) is the only thing that should be in the
    sensitivity list. Any signals inside the clocked part of the process
    shouldn't be in the sensitivity list.

    The read process looks kind of strange with two edges of RD being used,
    it might not synthesize very well. I'd recommend something like this:

    aLow <= aLowOut when (RD = '0')
    else (others => 'Z');

    (where aLowOut replaces aLow in the mux)

    Something like that will be compatible with your tri-state buffer- the
    RD signal directly controls the output enable.

    Another note: the address is being clocked and not latched as the
    comments indicate, if it were latched there will be more time for
    address decoding (which may not be an issue if you're using a fast FPGA
    and slow 8051).
     
    jens, Feb 6, 2006
    #4
  5. Cazed

    Dave Pollum Guest

    Cazed wrote:
    > Hi,
    >
    > I'm trying to interface my fpga with a 8051-uC using the external memory
    > feature. My problem is that according to my simulations the bus does not
    > output anything back to aLow (aLow multiplexes low eight address bits and
    > bidirectional data) when I try to read...Writing data seems to be working
    > fine though...
    >
    > Code:
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    >
    >
    > entity interface is
    > port(
    > aHigh : in std_logic; --Address MSB only one bit needed
    > aLow : inout std_logic_vector(7 downto 0); --Address LSB
    > ALE : in std_logic; --adress latch
    > WE : in std_logic; --Write enable
    > RD : in std_logic; --Read data
    > --Internal registers
    > RAMctrl : buffer std_logic_vector(1 downto 0);
    > RAMaddress : buffer std_logic_vector(5 downto 0);
    > RAMdata : buffer std_logic_vector(12 downto 0));
    > end interface;
    >
    >
    > architecture behave of interface is
    > signal address : std_logic_vector(8 downto 0);
    > begin
    > --latch in address
    > process(aHigh, aLow, ALE)
    > begin
    > if falling_edge(ALE) then --Latch in address
    > address(8) <= aHigh;
    > address(7 downto 0) <= aLow;
    > end if;
    > end process;
    >
    > process(address, WE)
    > begin
    > if rising_edge(WE) then --write to register
    > case address is
    > when "100000000" => NULL; --STATUS
    > when "110000001" => RAMdata(7 downto 0) <= aLow;
    > --CRDLSB
    > when "110000010" => RAMdata(12 downto 8) <=aLow(4 downto
    > 0);--CRDMSB
    > when "110000011" => RAMaddress <= aLow(5 downto 0);
    > --CRADDRESS
    > when "110000000" => RAMctrl <= aLow(1 downto 0);
    > --CRCONTROL
    > when OTHERS => NULL;
    > end case;
    > end if;
    > end process;
    >
    > process(address, RD)
    > begin
    > if falling_edge(RD) then
    > case address is
    > when "100000000" => NULL; --STATUS
    > when "110000001" => aLow <= RAMdata(7 downto 0);
    > --CRDLSB
    > when "110000010" => aLow(4 downto 0) <= RAMdata(12 downto
    > 8);--CRDMSB
    > when "110000011" => aLow(5 downto 0) <= RAMaddress;
    > when "110000000" => aLow(1 downto 0) <= RAMctrl;
    > when OTHERS => NULL;
    > end case;
    > end if;
    > if rising_edge(RD) then
    > aLow <= "ZZZZZZZZ";
    > end if;
    > end process;
    > end behave;
    >
    > Does the simulated input be anything special to allow the readprocess to
    > output data on aLow?
    >
    > Regards
    > /Åke "Cazed" Forslund


    I'm curious what aLow is assigned when the "others" statement is
    executed. Does garbage get assigned to aLow?

    When creating code to read registers, I've used something like this
    ("data" is "inout"):

    process ( address, rd ) is
    begin
    data <= (others => 'Z');
    if rd = '1' then
    case address is
    when "00" => data <= reg1;
    when "01" => data <= reg2;
    when "10" => data <= reg3;
    when others => null;
    end case;
    end if;
    end process;

    -Dave Pollum
     
    Dave Pollum, Feb 7, 2006
    #5
  6. Cazed

    Cazed Guest

    Hi, and thanks for all the help,

    I solved the initial problem and it was really located about 40 cm from
    the screen ;). I seemed to have forgotten to unfreeze the signal aLow in
    my simulation making any readable data on the port invisible.

    However, I still get a bunch of warnings and I will check out all tips I
    have gotten here.

    Regards
    /Åke Forslund

    P.S. I apologize for mangling technical terms such as "Latch", I asdumed
    the data was "Latched" since the signal ALE is described as a latch. I
    will promptly look up the difference between clock and latch. D.S.
     
    Cazed, Feb 8, 2006
    #6
  7. Cazed

    Guest

    Hi Jens,

    after dealing with some other issues I returned to the 8051-interface
    earlier today, looked at your recommendation, checked out the syntax in
    my book, and finally saw how to use yor recommendation!

    Now the module synthesises without any warnings and simulates
    perfectly,

    Thanks for the help!

    /Åke "Cazed" Forslund
     
    , Mar 1, 2006
    #7
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