Problems with multiple events

Discussion in 'VHDL' started by pflloyd, Feb 3, 2005.

  1. pflloyd

    pflloyd Guest

    I am using Quartus II to create a VHDL program for an Altera
    EPM7064STC100-10. I have several three different processees: one controls
    a state machine, one generates interrupts, and one validates/invalidates
    stored data. One process looks like the following:

    process(clk, Reset)
    begin
    if Reset = '1' then
    -- reset
    elsif clk'event and clk = '1' then
    -- Code here
    end if;
    end process;

    Another process looks like this:

    process(Reset, DataSentTouCAck, Latch_FMU_Bus)
    variable temp : bit;
    begin
    if Reset = '1' then
    temp := '0';
    elsif DataSentTouCAck'event and DataSentTouCAck = '1' then
    temp := '0';
    elsif Latch_FMU_Bus = '1' then
    temp := '1';
    end if;
    DataInLatchToFMUValid <= temp;
    end process;

    When I compile this I get the following error

    Can't infer register for signal "temp" because signal does not hold its
    value outside clock edge

    This process is just a D-FF with an asynchronous reset.

    If I remove the 'DataSentToFMUAck'event' statement it will compile. I
    know the process will be level sensitive instead of edge sensitive, but I
    should be able to have two different edge sensitive processes in my
    program.

    Am I getting this error because the CPLD this is being compiled for is
    limited in resources? Any ideas would be great. Thanks.
    pflloyd, Feb 3, 2005
    #1
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  2. pflloyd wrote:


    > process(Reset, DataSentTouCAck, Latch_FMU_Bus)
    > variable temp : bit;
    > begin
    > if Reset = '1' then
    > temp := '0';
    > elsif DataSentTouCAck'event and DataSentTouCAck = '1' then
    > temp := '0';
    > elsif Latch_FMU_Bus = '1' then
    > temp := '1';
    > end if;
    > DataInLatchToFMUValid <= temp;
    > end process;
    >
    > When I compile this I get the following error
    >
    > Can't infer register for signal "temp" because signal does not hold its
    > value outside clock edge
    >
    > This process is just a D-FF with an asynchronous reset.


    process(Reset, DataSentTouCAck, Latch_FMU_Bus)
    variable temp : bit;
    begin
    if Reset = '1' then
    temp := '0';
    elsif Latch_FMU_Bus = '1' then
    temp := '1';
    elsif DataSentTouCAck'event and DataSentTouCAck = '1' then
    temp := '0';
    end if;
    DataInLatchToFMUValid <= temp;
    end process;

    Async set / rest is not allowed in an elsif branch after an 'event.

    Ralf
    Ralf Hildebrandt, Feb 3, 2005
    #2
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  3. Ralf Hildebrandt a écrit :

    > process(Reset, DataSentTouCAck, Latch_FMU_Bus)
    > variable temp : bit;
    > begin
    > if Reset = '1' then
    > temp := '0';
    > elsif Latch_FMU_Bus = '1' then
    > temp := '1';
    > elsif DataSentTouCAck'event and DataSentTouCAck = '1' then
    > temp := '0';
    > end if;
    > DataInLatchToFMUValid <= temp;
    > end process;
    >
    > Async set / rest is not allowed in an elsif branch after an 'event.


    Not sure this will compile either, if the EPM doesn't have FFs with both
    async set and preset.


    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
    Nicolas Matringe, Feb 3, 2005
    #3
  4. pflloyd wrote:
    > process(Reset, DataSentTouCAck, Latch_FMU_Bus)
    > variable temp : bit;
    > begin
    > if Reset = '1' then
    > temp := '0';
    > elsif DataSentTouCAck'event and DataSentTouCAck = '1' then
    > temp := '0';
    > elsif Latch_FMU_Bus = '1' then
    > temp := '1';
    > end if;
    > DataInLatchToFMUValid <= temp;
    > end process;
    >
    > When I compile this I get the following error
    >
    > Can't infer register for signal "temp" because signal does not hold its
    > value outside clock edge
    >
    > This process is just a D-FF with an asynchronous reset.


    Could you draw me a picture of what you're trying to build, because this
    most certainly does not look like a D-FF. On the positive clock edge you
    want temp to become 0, and if there's no clock edge you want it to become 1
    if latch_fmu_bus = 1. I can imagine that the compiler doesn't know what to
    build out of this.

    Regards,

    Pieter Hulshoff
    Pieter Hulshoff, Feb 3, 2005
    #4
  5. pflloyd

    scottypc Guest

    You need to seriously consider taking a VHDL for beginners class. That
    code is terrible.
    scottypc, Feb 3, 2005
    #5
  6. > process(Reset, DataSentTouCAck, Latch_FMU_Bus)
    > variable temp : bit;
    > begin
    > if Reset = '1' then
    > temp := '0';
    > elsif DataSentTouCAck'event and DataSentTouCAck = '1' then
    > temp := '0';
    > elsif Latch_FMU_Bus = '1' then
    > temp := '1';
    > end if;
    > DataInLatchToFMUValid <= temp;
    > end process;


    You might want to look at your prioritisation - this can make a difference.

    If you wrote it like:

    process(Reset, DataSentTouCAck, Latch_FMU_Bus)
    begin
    if Reset = '1' then
    DataInLatchToFMUValid <= '0';
    elsif Latch_FMU_Bus = '1' then
    DataInLatchToFMUValid <= '1';
    elsif DataSentTouCAck'event and DataSentTouCAck = '1' then
    DataInLatchToFMUValid <= '1';
    end if;
    end process;

    Then it should work. I haven't tested it, and it will depend on whether
    the device in question has D FFs w/ async preset and clear (as another
    poster commented). This pretty much matches the inference code in the
    Xilinx libraries guide for the D FF w/ sync. preset and clear, with the
    D input pulled to Vcc, so I'd have confidence in it's general
    synthesizability.

    Of course, this makes assumptions about what you actually want to *do*.

    Jeremy
    Jeremy Stringer, Feb 4, 2005
    #6
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