Problems with SRAM controller

Discussion in 'VHDL' started by bittor, Dec 22, 2004.

  1. bittor

    bittor Guest

    Hello,
    I must do a symple controller for SRAM in VHDL. I must write datas and
    after read these datas. I have problems with bidirectional port. Someone
    has a similar design or an idea for doing this?
    Thanks
     
    bittor, Dec 22, 2004
    #1
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  2. bittor

    Guest

    You can three registers such as Data_in, Data_out and Data. Then you
    must use tri-state

    Data <= Data_out when RamW = '1' else (others => 'Z' );
    Data_in <= Data when RamR = '1' else (others => '0');
     
    , Dec 23, 2004
    #2
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  3. bittor

    bittor Guest

    Thanks usrdr,
    That's what I've done and now all is running well.
    Happy new year!!
     
    bittor, Dec 23, 2004
    #3
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