problems with time simulation

Discussion in 'VHDL' started by kd17, Apr 14, 2010.

  1. kd17

    kd17

    Joined:
    Apr 14, 2010
    Messages:
    2
    Hi,
    I try make time simulation of following code:
    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    entity vld is
       port(stop_in : in std_logic;
              stop_out : out std_logic
             );
    end vld;
    
    architecture Behavioral of vld is
    
    component buf_delay is
    	generic(delay : time
    	          );
    	port(in_sig : in std_logic;
    	      out_sig : out std_logic
    	     );
    end component;
    
    signal stop_sig : std_logic_vector(3 downto 0);
    
    begin
    
       stop_sig(0) <= stop_in;
    
       buf_stop0 : buf_delay 
          generic map(delay => 650 ps
                     )
          port map(in_sig => stop_sig(0),
                   out_sig => stop_sig(1)
                  );
       buf_stop1 : buf_delay 
          generic map(delay => 750 ps
                     )
          port map(in_sig => stop_sig(1),
                   out_sig => stop_sig(2)
                  );
       buf_stop2 : buf_delay 
          generic map(delay => 850 ps
                     )
          port map(in_sig => stop_sig(2),
                   out_sig => stop_sig(3)
                  );
    
       stop_out <= stop_sig(3);
    end Behavioral;
    
    The buf_delay component look that:
    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    entity buf_delay is
    	generic(delay : time := 100 ps
    			 );
    	port(in_sig : in std_logic;
    		  out_sig : out std_logic
    		 );
    end buf_delay;
    
    architecture Behavioral of buf_delay is
    
    begin
    
    	out_sig <= in_sig after delay;
    
    end Behavioral;
    
    And testbench look that:
    Code:
    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.std_logic_unsigned.all;
    USE ieee.numeric_std.ALL;
     
    ENTITY vdl_tb IS
    END vdl_tb;
     
    ARCHITECTURE behavior OF vdl_tb IS 
     
        -- Component Declaration for the Unit Under Test (UUT)
     
        COMPONENT vld
        PORT(
             stop_in : IN  std_logic;
             stop_out : OUT  std_logic
            );
        END COMPONENT;
        
    
       --Inputs
       signal stop_in : std_logic := '0';
    
     	--Outputs
       signal stop_out : std_logic;
       
     
    BEGIN
     
    	-- Instantiate the Unit Under Test (UUT)
       uut: vld PORT MAP (
              stop_in => stop_in,
              stop_out => stop_out
            );
     
       -- No clocks detected in port list. Replace <clock> below with 
       -- appropriate port name 
     
    
    
       -- Stimulus process
       stim_proc: process
       begin		
          -- hold reset state for 100ms.
          stop_in <= '0';
          wait for 10ns;	
          wait for 150ps;
          stop_in <= '1';
          
          -- insert stimulus here 
    
          wait;
       end process;
    
    END;
    
    Result of this simulation should be that:
    '1' appear on stop_sig(0) at 10150 ps,
    next the same '1' appear on stop_sig(1) at 10800 ps,
    next '1' appear on stop_sig(2) at 11550 ps
    and the last '1' should appear on stop_sig(3) at 12400 ps.
    But results of simulation are that:
    stop_sig(0) is '1' after 10150 ps,
    stop_sig(1) is '1' after 11000 ps,
    stop_sig(2) is '1' after 11850 ps,
    stop_sig(3) is '1' after 12700 ps,
    So somthing is wrong with param delay from buf_delay. Only the last is take into account. Thx for any help.

    Kd17
    kd17, Apr 14, 2010
    #1
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