Procedure calls in process

[Sylvain Munaut]

Hello all,

I'm trying to understand a weird behavior I'm observing in the simulator.
First I must say it's for a test bench so I don't "really" care about
optimality or synthesis.

I'm calling a procedure from a continuous process (no sensitivitylist) and
the result for the first "iteration" is not what I expect, while all the
others are OK.

The result can be seen here :

http://www.246tnt.com/files/wave.png

It shows two runs of the process that I would expect to be identical ... I've run
the simulation thru both modelsim and simili with same results.

Here is the code snippet : (note it's just a test, not at all real PCI ... )

-- PCI Scenario
process

type dataseq_t is array(integer range <>) of std_logic_vector(31 downto 0);

-- PCI Read sequence

-- PCI Write sequence
procedure pci_do_write(
w : in integer;
data : in test_t
) is
begin
pci_frame_n <= '0';
pci_ad <= data(0);
wait for 100 ns;
pci_frame_n <= '1';
pci_ad <= data(1);
wait for 100 ns;
pci_frame_n <= 'Z';
pci_ad <= data(2);
end procedure;

constant ts : dataseq_t(0 to 2) := ( x"12345678", x"9ABCDEF0", x"13FF005A" );
begin

-- Reset
wait for 10 ns;
pci_do_write(2, ts);
wait for 200 ns;

end process;


Thanks for any insight ...

Sylvain

 

[Jim Lewis]

Sylvain,
Is there another driver of pci_ad? Looks to me like there
is and it is not turned tristated until well into your
first pci write cycle. One thing you may want to try is
initializing all sources for pci_ad to all 'Z'.

Regards,
jim

Hello all,

I'm trying to understand a weird behavior I'm observing in the simulator.
First I must say it's for a test bench so I don't "really" care about
optimality or synthesis.

I'm calling a procedure from a continuous process (no sensitivitylist) and
the result for the first "iteration" is not what I expect, while all the
others are OK.

The result can be seen here :

http://www.246tnt.com/files/wave.png

It shows two runs of the process that I would expect to be identical ...
I've run
the simulation thru both modelsim and simili with same results.

Here is the code snippet : (note it's just a test, not at all real PCI
... )

-- PCI Scenario
process

type dataseq_t is array(integer range <>) of std_logic_vector(31
downto 0);

-- PCI Read sequence

-- PCI Write sequence
procedure pci_do_write(
w : in integer;
data : in test_t
) is
begin
pci_frame_n <= '0';
pci_ad <= data(0);
wait for 100 ns;
pci_frame_n <= '1';
pci_ad <= data(1);
wait for 100 ns;
pci_frame_n <= 'Z';
pci_ad <= data(2);
end procedure;

constant ts : dataseq_t(0 to 2) := ( x"12345678", x"9ABCDEF0",
x"13FF005A" );
begin

-- Reset
wait for 10 ns;
pci_do_write(2, ts);
wait for 200 ns;

end process;


Thanks for any insight ...

Sylvain

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Sylvain Munaut]

Hi Jim

Is there another driver of pci_ad? Looks to me like there
is and it is not turned tristated until well into your
first pci write cycle. One thing you may want to try is
initializing all sources for pci_ad to all 'Z'.

Damn, I missed the obvious ! Since I was modifying my simple
test bench to make it more "advanced", I just forgot that there
was the PCI target core I'm working on plugged in ... And it
reacted to those "weird" test signals ...


Sylvain