Procedure VHDL

Discussion in 'VHDL' started by hilal, Mar 29, 2008.

  1. hilal

    hilal

    Joined:
    Mar 13, 2008
    Messages:
    5
    Hi,

    I am trying to make my test bench code look easier.

    So I tried to make a procedure like this:

    Code:
    procedure rw_tb(
            signal strb, rw : in std_logic;
    	signal io_adr, io_data : in std_logic_vector;
    	signal strb_o, rw_o : out std_logic;
    	signal io_adr_o, io_data_o: out std_logic_vector) is
    	begin
    		strb_o <= strb;
    		rw_o <= rw;
    		io_adr_o <= io_adr;
    		io_data_o <= io_data;
    	end rw_tb;
    
    and I tried to call it with:

    rw_tb('1', '1', X"10", X"7F7F", strb, rw, io_addr, io_data);

    but I get the following errors, why dose this not work?

    Code:
    ERROR:HDLParsers:3298 - "/home/monty/kurser/vlsi/project/project_with_xco/vlsi/../project/test_bench/hib_dcu_cnn_dist_values_tb.vhd" line 194. Expression is not a static name.
    ERROR:HDLParsers:3321 - "/home/monty/kurser/vlsi/project/project_with_xco/vlsi/../project/test_bench/hib_dcu_cnn_dist_values_tb.vhd" Line 194. Actual associated with Formal signal is not a static signal name. (LRM 2.1.1.2)
    ERROR:HDLParsers:3298 - "/home/monty/kurser/vlsi/project/project_with_xco/vlsi/../project/test_bench/hib_dcu_cnn_dist_values_tb.vhd" line 194. Expression is not a static name.
    ERROR:HDLParsers:3321 - "/home/monty/kurser/vlsi/project/project_with_xco/vlsi/../project/test_bench/hib_dcu_cnn_dist_values_tb.vhd" Line 194. Actual associated with Formal signal is not a static signal name. (LRM 2.1.1.2)
    ERROR:HDLParsers:3298 - "/home/monty/kurser/vlsi/project/project_with_xco/vlsi/../project/test_bench/hib_dcu_cnn_dist_values_tb.vhd" line 194. Expression is not a static name.
    ERROR:HDLParsers:3321 - "/home/monty/kurser/vlsi/project/project_with_xco/vlsi/../project/test_bench/hib_dcu_cnn_dist_values_tb.vhd" Line 194. Actual associated with Formal signal is not a static signal name. (LRM 2.1.1.2)
    ERROR:HDLParsers:3298 - "/home/monty/kurser/vlsi/project/project_with_xco/vlsi/../project/test_bench/hib_dcu_cnn_dist_values_tb.vhd" line 194. Expression is not a static name.
    ERROR:HDLParsers:3321 - "/home/monty/kurser/vlsi/project/project_with_xco/vlsi/../project/test_bench/hib_dcu_cnn_dist_values_tb.vhd" Line 194. Actual associated with Formal signal is not a static signal name. (LRM 2.1.1.2)
    
    thank you in advance
     
    hilal, Mar 29, 2008
    #1
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  2. hilal

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark

    Attached Files:

    Last edited: Mar 29, 2008
    jeppe, Mar 29, 2008
    #2
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  3. hilal

    hilal

    Joined:
    Mar 13, 2008
    Messages:
    5
    it is working, thank you :)

    thanks for the link.
     
    hilal, Mar 29, 2008
    #3
  4. hilal

    BernhardF

    Joined:
    Sep 3, 2008
    Messages:
    1
    hello,

    i have a similar error. maybe you can help me too.

    procedure test (
    signal input : in std_logic_vector;
    signal ctrl : in std_logic_vector(2 downto 0);
    signal output : out std_logic_vector;
    constant vector_bit : in integer range 0 to 31) is
    begin

    bla(input => input(vector_bit), ctrl => ctrl, output => output(0));

    end;

    passing the argument of output static works
    trying to pass the parameter of input with the constant integer produces an error

    Actual (indexed name) for formal "input" is not a static signal name.

    any ideas?
     
    BernhardF, Sep 3, 2008
    #4
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