procedure

Discussion in 'VHDL' started by Salman Sheikh, Sep 30, 2003.

  1. What is wrong with this?

    procedure gen_s (
    variable si, di : in std_logic_vector(z_width downto 0);
    variable so : out std_logic_vector(z_width downto 0)) is
    begin
    if si(z_width) = '1' then
    so := (si(z_width-1 downto 0) & '0') + di;
    else
    so := (si(z_width-1 downto 0) & '0' - di);
    end if;
    end gen_s;


    I get errors about the + and - being infix operators in Modelsim, below.

    # ** Error: C:/dividers/div_uu.vhd(72): No feasible entries for infix op: "+"
    # ** Error: C:/dividers/div_uu.vhd(72): Bad right hand side in assignment.
    # ** Error: C:/dividers/div_uu.vhd(74): No feasible entries for infix op: "-"
    # ** Error: C:/dividers/div_uu.vhd(74): Bad right hand side in assignment.


    Thanks.

    Salman
    Salman Sheikh, Sep 30, 2003
    #1
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  2. Salman Sheikh wrote:
    > What is wrong with this?
    >
    > procedure gen_s (
    > variable si, di : in std_logic_vector(z_width downto 0);
    > variable so : out std_logic_vector(z_width downto 0)) is
    > begin
    > if si(z_width) = '1' then
    > so := (si(z_width-1 downto 0) & '0') + di;
    > else
    > so := (si(z_width-1 downto 0) & '0' - di);
    > end if;
    > end gen_s;
    >
    >
    > I get errors about the + and - being infix operators in Modelsim, below.
    >
    > # ** Error: C:/dividers/div_uu.vhd(72): No feasible entries for infix op: "+"
    > # ** Error: C:/dividers/div_uu.vhd(72): Bad right hand side in assignment.
    > # ** Error: C:/dividers/div_uu.vhd(74): No feasible entries for infix op: "-"
    > # ** Error: C:/dividers/div_uu.vhd(74): Bad right hand side in assignment.
    >
    >
    > Thanks.
    >
    > Salman
    >


    Salman,

    You can't do calculations on a std_logic_vector. Try using signed or
    unsigned in stead.

    Kind regards,

    Yves
    Yves Deweerdt, Sep 30, 2003
    #2
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  3. Salman Sheikh wrote:
    > What is wrong with this?
    >
    > procedure gen_s (
    > variable si, di : in std_logic_vector(z_width downto 0);
    > variable so : out std_logic_vector(z_width downto 0)) is
    > begin
    > if si(z_width) = '1' then
    > so := (si(z_width-1 downto 0) & '0') + di;
    > else
    > so := (si(z_width-1 downto 0) & '0' - di);
    > end if;
    > end gen_s;


    Not too much.

    Add this to the top of your entity:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    and change std_logic_vector to unsigned.

    -- Mike Treseler
    Mike Treseler, Sep 30, 2003
    #3
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