process sentence in synthesis

Discussion in 'VHDL' started by Jluis, Apr 30, 2004.

  1. Jluis

    Jluis Guest

    hi vhdl group..!!!

    on the process sentence what do I have to put FOR SYNTHESIS?
    FOR EXAMPLE

    PORT(
    clk: IN std_logic; --CLOCK
    wIR: IN std_logic; --CONTROL SIGNAL
    datainIR: IN std_logic_vector(21 DOWNTO 0);
    Aout,Bout: OUT std_logic_vector(2 DOWNTO 0)
    );

    ARCHITECTURE archinst OF inst IS
    BEGIN
    PROCESS(clk)
    BEGIN
    OR
    ARCHITECTURE archinst OF inst IS
    BEGIN
    PROCESS(clk, wIR, datainIR)
    BEGIN

    ON THIS EXAMPLE i HAVE TO PUT ALL THE INPUTS PORT OR WHAT?

    THANKS IN ADVANCE.

    JLuis
     
    Jluis, Apr 30, 2004
    #1
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  2. Jluis a écrit:
    > hi vhdl group..!!!


    Hi

    [...]


    > ARCHITECTURE archinst OF inst IS
    > BEGIN
    > PROCESS(clk)
    > BEGIN
    > OR
    > ARCHITECTURE archinst OF inst IS
    > BEGIN
    > PROCESS(clk, wIR, datainIR)
    > BEGIN
    >
    > ON THIS EXAMPLE i HAVE TO PUT ALL THE INPUTS PORT OR WHAT?


    (please don't shout, we're not deaf)
    It all depends on what you do in your process. Usually, clocked
    processes need only the clock (and the reset when it is asynchronous)
    put in the sensitivity list.

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Apr 30, 2004
    #2
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  3. Jluis wrote:


    > PORT(
    > clk: IN std_logic; --CLOCK
    > wIR: IN std_logic; --CONTROL SIGNAL
    > datainIR: IN std_logic_vector(21 DOWNTO 0);
    > Aout,Bout: OUT std_logic_vector(2 DOWNTO 0)
    > );
    >
    > ARCHITECTURE archinst OF inst IS
    > BEGIN
    > PROCESS(clk)
    > BEGIN
    > OR
    > ARCHITECTURE archinst OF inst IS
    > BEGIN
    > PROCESS(clk, wIR, datainIR)
    > BEGIN
    >
    > ON THIS EXAMPLE i HAVE TO PUT ALL THE INPUTS PORT OR WHAT?



    In the sensitivity list of a process (the signals in parenthesis) all
    signals have to be put in, that are read in this process. It does not
    matter if these are input signals or internal signals.


    Exception: If you write a syncronous process (flipflop), all asyncronous
    signals and the clock-signal have to be put into the sensitivity list.
    Example:

    process(reset,set,clock)
    begin
    if (set='1') then
    out_signal<='1';
    elsif (reset='1') then
    out_signal<='0';
    elsif rising_edge(clock) then
    out_signal<=(in_signal1 AND in_signal2) XOR in_signal3;
    end if;
    end process;

    Note: in_signal1, in_signal2 and in_signal3 do not appear in the
    sensitivity list (although being read), because they are read only at
    rising_edge(clock). Therefore it is useless to activate the process, if
    in_signal1, in_signal2 or in_signal3 changes.



    For all other processes (that model combinational logic or latches) the
    1st statement holds: "Put all signals in the sensitivity list, that are
    being read in the process."
    Example - comb. logic:

    process(in_signal1,in_signal2,in_signal3)
    begin
    out_signal<=(in_signal1 AND in_signal2) XOR in_signal3;
    end process;


    Example - latch:

    process(latch_enable,in_signal1,in_signal2,in_signal3)
    begin
    if latch_enable='1') then
    out_signal<=(in_signal1 AND in_signal2) XOR in_signal3;
    end if;
    end process;


    Ralf
     
    Ralf Hildebrandt, Apr 30, 2004
    #3
  4. Jluis

    Riyaz Guest

    This depends on which signals the process is reading. You only supply those
    inputs to the process statement that the process is 'sensitive' to, i.e.
    those signals that are used in the process.

    "Jluis" <> wrote in message
    news:...
    > hi vhdl group..!!!
    >
    > on the process sentence what do I have to put FOR SYNTHESIS?
    > FOR EXAMPLE
    >
    > PORT(
    > clk: IN std_logic; --CLOCK
    > wIR: IN std_logic; --CONTROL SIGNAL
    > datainIR: IN std_logic_vector(21 DOWNTO 0);
    > Aout,Bout: OUT std_logic_vector(2 DOWNTO 0)
    > );
    >
    > ARCHITECTURE archinst OF inst IS
    > BEGIN
    > PROCESS(clk)
    > BEGIN
    > OR
    > ARCHITECTURE archinst OF inst IS
    > BEGIN
    > PROCESS(clk, wIR, datainIR)
    > BEGIN
    >
    > ON THIS EXAMPLE i HAVE TO PUT ALL THE INPUTS PORT OR WHAT?
    >
    > THANKS IN ADVANCE.
    >
    > JLuis
     
    Riyaz, May 5, 2004
    #4
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