Protected simulation models

Discussion in 'VHDL' started by devices, Sep 10, 2006.

  1. devices

    devices Guest

    I found some protected verilog simulation models.
    (Base64 like text files) I'm not interested in viewing the sources.
    But before i spend some time in including them in a
    simulation, i'd like to know whether development
    environtments like Ise WebPack can work with them.

    And if the answer is Yes, what extension do those file
    need to have? ".v" anyway ? Can i drive them with vhdl
    code?

    nice day
     
    devices, Sep 10, 2006
    #1
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  2. devices

    devices Guest

    I guess this says it all

    http://www.fourelectronics.com/Can-Verilog-codes-be-synthesized-with-XIlinx-XST-3431265.html

    "devices" <me@home> wrote in message
    news:450452eb$0$17455$...
    > I found some protected verilog simulation models.
    > (Base64 like text files) I'm not interested in viewing the sources.
    > But before i spend some time in including them in a
    > simulation, i'd like to know whether development
    > environtments like Ise WebPack can work with them.
    >
    > And if the answer is Yes, what extension do those file
    > need to have? ".v" anyway ? Can i drive them with vhdl
    > code?
    >
    > nice day
    >
    >
    >
     
    devices, Sep 11, 2006
    #2
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