PSL: New 2nd Edition book: Using PSL for formal and dynamic verification

Discussion in 'VHDL' started by ben cohen, Jan 27, 2004.

  1. ben cohen

    ben cohen Guest

    We am pleased to announce the release of the book "Using PSL/SUGAR for
    Formal and Dynamic Verification 2nd Edition". Site provides information about this book,
    including the TOC, forewords by Harry Foster, Cadence, Mentor, @HDL,
    and Safelogic. Every reviewer highly recommended this book for
    designer and verification engineers who write PSL. "Through coding
    guidelines, easily understood descriptions of the language semantics
    and real world examples, the authors ease the transition into
    successful, productive use of PSL... the preferred PSL bible."

    PSL is a property specification language that can be used for the
    definition of requirements (including system level), interface
    definitions, design properties, and for the verification of designs
    using dynamic and model checking techniques. The book addresses PSL
    language, and demonstrates by example how PSL is applied in the design
    definition and verification processes. Several VHDL and Verilog
    models are used as vehicles to demonstrate the efficiency of PSL.
    These include a FIFO, a handshake, an AMBA AHB slave, and a traffic
    light controller. One chapter is dedicated to formal verification,
    and another one to PSL guidelines. Appendix D provides a dictionary
    of classes of application examples that translate English requirements
    to PSL properties.

    I am also please to announce that I'll be giving 3-hour PSL tutorials
    at DesignCon ( and DvCon ( Those tutorials
    are based on our book. Tutorials will include an explanation of the
    language, its applications, and demonstrations of practical examples
    for the definition of requirements, and in verification of designs
    using dynamic and formal verification techniques.

    Mentor is sponsoring the PSL DvCon tutorial, which brings down the
    price to $50 from $200. Coffee and pastries are included!

    Ben Cohen, Srinivasan Venkataramanan and Ajeetha Kumari.

    Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
    Author of following textbooks:
    * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition,
    2004 isbn 0-9705394-6-0
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
    ben cohen, Jan 27, 2004
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