Hi KVM,
From my limited exposure to the language (I've just done an introduction
course),
Pros:
1) Very powerful formal language, or assert statement on steroid for
hardware engineers
2) Easy to learn, most of the constructs are logical.
3) Most EDA vendors seem to support it.
4) There are even some vendors which can translate your embedded PSL
constructs into hardware monitor.
5) PSL can be embedded in your code (hardware engineer) or put into a
separate vunit (verification engineer).
6) PSL is a full formal language, a subset can be used in dynamic
simulation.
Cons:
1) Only supported by high-end $$$ EDA tools (like Modelsim SE) which will
limit its uptake.
2) During my PSL course I felt that I needed another language to check my
PSL.
3) Easy to create spaghetti code (unreadable constructs).
4) Requires a different mindset, i.e. engineer who do not use assert
statements (other than to stop the simulator) or never heard of OVL will not
use it.
5) They created different flavoured version for VHDL and Verilog, so you can
not write generic PSL. It shouldn't be too difficult to write a translator
between the two flavours but I have seen it yet.
6) Some EDA vendors only support the Verilog flavour
If you want to learn language, get yourself onto a PSL course to make sure
you learn how to think in PSL, secondly get yourself a tool which can
generate VHDL from a drawn waveform, this will enable you to create simple
stimulus for your PSL assertions. Get Ben Cohen's book,
I definitely like the language and will use it for my next design,
Regards,
Hans.
www.ht-lab.com