pst translate simulation

Discussion in 'VHDL' started by priya, Sep 10, 2007.

  1. priya

    priya Guest

    Hello frens
    i had written some module in VHDL.
    I had verified the functionality of the module (Functional simulation-
    Modelsim).
    but after POST translation when i m simulating i m getting garbage
    value.
    wat cud be the problem i simply failed to figure out
    Priyanka
     
    priya, Sep 10, 2007
    #1
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  2. priya

    priya Guest

    i m sending u the code
    im getting corrct result after func sim
    but after post translation im getting last 8 bits incorrect
    pls reply back soon
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity mix_column is
    Port ( clk : in std_logic;
    rst : in std_logic;
    en : in std_logic;
    rdy : out std_logic;
    dump : out std_logic_vector(7 downto 0);
    data : out std_logic_vector(31 downto 0));
    end mix_column;

    architecture Behavioral of mix_column is
    -------------------------------------------
    component
    llut --
    8 bit LUT rising edge trigger
    port (
    addr: IN std_logic_VECTOR(7 downto 0);
    clk: IN std_logic;
    dout: OUT std_logic_VECTOR(7 downto 0);
    en: IN std_logic;
    nd: IN std_logic;
    rfd: OUT std_logic;
    rdy: OUT std_logic;
    sinit: IN std_logic);
    end component;
    -------------------------------------------
    component e_lut --falling
    edge
    trigger 8 bit LUT
    port (
    addr: IN std_logic_VECTOR(7 downto 0);
    clk: IN std_logic;
    dout: OUT std_logic_VECTOR(7 downto 0);
    en: IN std_logic;
    nd: IN std_logic;
    rfd: OUT std_logic;
    rdy: OUT std_logic;
    sinit: IN std_logic);
    end component;

    signal temp_out : std_logic_vector(23 downto 0);
    signal prod : std_logic_vector(15 downto 0);
    signal temp_a, temp_b : std_logic_vector(7 downto 0);
    signal inp_a, inp_b, inp_c, inp_d : std_logic_vector(7 downto 0);
    signal result_a, result_b :std_logic_vector(7 downto 0);
    signal enable_la, enable_lb, enable_lab, enable_eab, nd_l, nd_ea,
    nd_eb :
    std_logic;
    signal rdy_la, rdy_lb, rdy_ea, rdy_eb : std_logic;
    signal i, k : is integer range 0 to 15;
    signal t, n, m, j : is integer range 0 to 3;
    signal temp_buffer : is array(0 to 15) of std_logic_vector(7 downto
    0);
    signal mix, sinit, sinit_e,flg :std_logic;

    begin

    Alogtable_a : e_lut
    port map (
    addr => temp_a,
    clk => clk,
    dout => result_a,
    en => enable_eab,
    nd => nd_ea,
    rdy => rdy_ea,
    sinit => sinit_e);
    Alogtable_b : e_lut
    port map (
    addr => temp_b,
    clk => clk,
    dout => result_b,
    en => enable_eab,
    nd => nd_eb,
    rdy => rdy_eb,
    sinit => sinit_e);
    Logtable_a : llut
    port map (
    addr => inp_a,
    clk => clk,
    dout => prod(7 downto 0),
    en => enable_lab,
    nd => nd_l,
    rdy => rdy_la,
    sinit => sinit);
    Logtable_b : llut
    port map (
    addr => inp_b,
    clk => clk,
    dout => prod(15 downto 8),
    en => enable_lab,
    nd => nd_l,
    rdy => rdy_lb,
    sinit => sinit);
    process(clk,rst,en)
    begin
    if rst ='0' then
    enable_lab <= '1';
    i <= 0;
    n <= 0;
    j <= 0;
    m <= 0;
    nd_l <= '0';
    mix <= '0';
    rdy <= '0';
    sinit <= '1';
    inp_a <= (others => '0');
    inp_b <= (others => '0');
    data <= (others => '0');
    temp_out <= (others => '0');
    temp_buffer <=((0)=>x"1A",(1)=>x"48",(2)=>x"2B",
    (3)=>x"D6",

    (4)=>x"28",(5)=>x"9B",(6)=>x"DC",(7)=>x"54",

    (8)=>x"B4",(9)=>x"B8",(10)=>x"85",(11)=>x"5F",

    (12)=>x"AF",(13)=>x"F6",(14)=>x"A8",(15)=>x"66");
    -- temp_buffer <=((0)=>(others => '0'),
    (1)=>(others =>
    '0'),
    -- (2)=>(others => '0'),(3)=>(others =>
    '0'),
    --
    (4)=>(others => '0'),(5)=>(others => '0'),
    --
    (6)=>(others => '0'),(7)=>(others => '0'),
    --
    (8)=>(others => '0'),(9)=>(others => '0'),
    --
    (10)=>(others => '0'),(11)=>(others => '0'),
    --
    (12)=>(others => '0'),(13)=>(others => '0'),
    --
    (14)=>(others => '0'),(15)=>(others => '0'));

    elsif clk = '1' and clk'event then
    if en ='0' then
    sinit <= '0';
    -- if mix = '1' then
    nd_l <= '1';
    if rdy_ea = '1' and rdy_eb = '1'
    then
    if n = 0 then
    dump<= result_a xor
    result_b
    xor inp_c xor inp_d;
    end if;
    if n = 3 then
    if j = 3 then
    sinit <=
    '1';
    else
    n <= 0;
    j <= j
    + 1;
    end if;
    data(31 downto
    24)
    <= result_a xor result_b xor inp_c xor inp_d;
    data(23 downto
    0) <=
    temp_out(23 downto 0);
    rdy <= '1';
    else
    flg <= '1';
    rdy <= '0';
    n <= n + 1;
    temp_out((8*n
    +7)
    downto 8*n) <= result_a xor result_b xor inp_c xor inp_d;
    end if;
    end if;
    if i = 12 then

    if m < 3 then
    i <= 0;
    m <= m + 1;
    end if;
    else
    enable_la <= '1';
    enable_lb <= '1';
    enable_lab <= '1';
    i <= i + 4;
    end if;

    inp_a <= temp_buffer(i + m);
    inp_b <= temp_buffer(((m+1)mod
    4)+i);
    -- end if;
    -- else
    -- temp_buffer(i) <= data_in(7 downto 0);
    -- temp_buffer(i+4) <= data_in(15 downto
    8);
    -- temp_buffer(i+8) <= data_in(23 downto
    16);
    -- temp_buffer(i+12) <= data_in(31 downto
    24);
    -- if i < 3 then
    -- i <= i + 1;
    -- else
    -- mix <= '1';
    -- i <= 0;
    --
    -- end if;
    -- end if;
    else
    nd_l <= '0';
    i <= 0;
    n <= 0;
    m <= 0;
    mix <= '0';
    rdy <= '0';
    j <= 0;
    sinit <= '1';
    inp_a <= (others => '0');
    inp_b <= (others => '0');
    end if;
    end if;
    end process;
    process(clk,rst,en)
    begin
    if rst ='0' then
    enable_eab <= '1';
    t <= 0;
    k <= 0;
    nd_ea <= '0';
    nd_eb <= '0';
    sinit_e <= '1';
    inp_d <= (others => '0');
    inp_c <= (others => '0');
    temp_a <= (others => '0');
    temp_b <= (others => '0');
    elsif clk='0' and clk'event then
    if en ='0' then
    sinit_e <= '0';
    if rdy_la = '1' or rdy_lb = '1' then
    enable_eab <= '1';

    if nd_ea = '1' or nd_eb = '1' then
    inp_c <= temp_buffer(((t +
    2)mod
    4)+k);
    inp_d <= temp_buffer(((t +
    3)mod
    4)+k);

    if k = 12 then

    if t < 3 then
    k <= 0;
    t <= t + 1;
    end if;
    else
    k <= k + 4 ;
    end if;
    end if;
    end if;
    if rdy_la = '1' then
    if temp_buffer(i) = 0 then
    temp_a <= (others => '0');
    nd_ea <= '0';
    else
    nd_ea <= '1';
    if ( prod(7 downto 0) > x"E6")
    then
    temp_a <= x"19" +
    prod(7
    downto 0) + '1';
    else
    temp_a <= x"19" + prod(7
    downto
    0);
    end if;
    end if;
    end if;
    if rdy_lb = '1' then
    if temp_buffer(i+1) = 0 then
    temp_b <= (others => '0');
    nd_eb <= '0';
    else
    nd_eb <= '1';
    if ( prod(15 downto 8) >
    x"FE") then
    temp_b<= x"01" + prod(15
    downto 8)
    + '1';
    else
    temp_b<= x"01" + prod(15
    downto
    8);
    end if;


    end if;
    end if;
    else
    nd_ea <= '0';
    nd_eb <= '0';
    t <= 0;
    k <= 0;
    inp_d <= (others => '0');
    inp_c <= (others => '0');
    temp_a <= (others => '0');
    temp_b <= (others => '0');
    sinit_e <= '1';

    end if;
    end if;
    end process;
    end Behavioral;
    priya wrote:
    > Hello frens
    > i had written some module in VHDL.
    > I had verified the functionality of the module (Functional simulation-
    > Modelsim).
    > but after POST translation when i m simulating i m getting garbage
    > value.
    > wat cud be the problem i simply failed to figure out
    > Priyanka
     
    priya, Sep 10, 2007
    #2
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