Interesting, but the code is legal VHDL!
The condition, in the IF statement, is true when pc_reload is smaller or
equal then '1'
(It is NOT a signal assugnment)
Although the type of pc_reload is not shown I think for the type you used
'0' is smaller then '1' and '1' is equal then '1'. So the condition is, for
synthesis, always true.
I think the design is not simulated before it was synthesised. You would
have noticed that the else part also was not executed.
Try the following complete example. For simulation the output is always
equal to inst1 indpendent of pc_reload and inst2. And that is also what your
synthesis tool will produce .. only wires between inst1 and pc_reg.
Try to simulate this one:
entity demo is
port (pc_reload : bit;
inst1 : integer;
inst2 : integer;
pc_reg : out integer);
end demo;
architecture condition_check of demo is
begin
process(pc_reload, inst1, inst2)
begin
if pc_reload<='1' then
pc_reg<=inst1;
else
pc_reg<=inst2;
end if;
end process;
end condition_check ;
Egbert Molenkamp