Quartus II Warning: Found pins functioning as undefined clocks

Discussion in 'VHDL' started by Markus Jochim, May 29, 2007.

  1. Hello,

    I use Quartus II WebEdition 7.0 and have a simple design where the
    signal mclk takes the role of the clock.


    ENTITY Prescaler_50M_1 IS
    PORT (
    mclk: IN std_logic;
    c1Hz: OUT std_logic
    );
    END Prescaler_50M_1;


    The "Classic Timing Analyser Tool" complains:


    Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "mclk" is an undefined clock


    I looked this up in the Quartus II Handbook and found that it should
    help to define "mclk" to be a base clock by either a Tcl command like:

    create_base_clock -fmax 20ns -target mclk sys_clk

    or by defining an absolute clock associated with node "mclk" by using
    the GUI of Quartus II at the menu item "Assignments|Timing Analysis
    Settings|Classig Timing Analyser Settings|Individual Clocks"


    Unfortunately both ways do not work and the warning still appears.

    Can someone help???

    Best regards
    Markus
    Markus Jochim, May 29, 2007
    #1
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  2. Markus Jochim

    Guest

    I had this same problem, and I went to the Classic Timing Analyzer
    Settings tab, clicked Individual Clocks, and added a new entry. The
    name is arbitrary (refclk in my case) but "Applies to Node" must be
    set to the clock giving the warning. So I clicked on the List button,
    found my clock pin in the list (CPLD_REFCLK), added it, and clicked
    OK. When I recompiled the warning went away. Perhaps you weren't
    selecting the same "mclk" node that was triggering the warning? Do you
    have other instances of "mclk" in your design? Mine was an external
    pin so maybe it's different, but I can verify that this method does
    work in Web Edition 7.0.
    , Jun 1, 2007
    #2
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