Quartus not producing logic question

Discussion in 'VHDL' started by kipman725, Dec 14, 2008.

  1. kipman725

    kipman725 Guest

    Hello I'm trying to make a pong game I made the following module, it
    takes input from counters that increment to 766 in the x direction
    then reset and increment one in the y untill y reaches 512. There is
    another module generating Horizontal and vertical sync from this.
    This particular module is ment to be generating x and y position
    counters for the 640*480 play area and also an output that is high
    when the current position in the frame is in the play area, thereby
    simplifying the actual game logic. The problem is that I get
    "Warning: Following 20 pins have nothing, GND, or VCC driving datain
    port" and no logic is produced for this module. It acts like the x
    and y position counters for the frame can never meet the conditions of
    the if statments!?!?!
    My code is probobly horible I am self taught and quite inexperianced.
    I am using quartus 8.1 to compile this:

    --Game Position Counters
    --640*480 Pix play feild
    library ieee ;
    use ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.ALL;
    USE ieee.std_logic_signed.ALL;
    USE ieee.std_logic_unsigned.ALL;
    use work.all;

    entity gpc is
    port( clk: in std_logic;
    x : in std_logic_vector (9 DOWNTO 0); -- Frame x position
    y : in std_logic_vector (8 DOWNTO 0); -- Frame y position
    xgame : out std_logic_vector (9 DOWNTO 0); --Game x position
    ygame : out std_logic_vector (8 DOWNTO 0); --Game y position
    disable: out std_logic --Turns off r,g,b when not in play feild
    );
    END gpc;

    ARCHITECTURE behav of gpc is
    SIGNAL xgame_temp : std_logic_vector (9 DOWNTO 0);
    SIGNAL ygame_temp : std_logic_vector (8 DOWNTO 0);
    SIGNAL px, py : std_logic;
    begin
    process(clk, x, y)
    begin
    if (clk='1' and clk'event) then -- rising edge triggered
    if (x>71 and x<712) then -- y counter and range check
    xgame_temp <= (xgame_temp + 1);
    px <= '1'; -- x play area indicator
    else
    px <= '0';
    xgame_temp <= "0000000000"; -- reset
    end if;
    if (y>16 and y<497) then -- y counter and range check
    if (x = 713) then -- Only inc y play at end of line scan
    ygame_temp <= (ygame_temp + 1);
    end if;
    py <= '1';
    else
    py <= '0';
    ygame_temp <= "000000000"; -- reset
    end if;
    end if;
    end process;
    disable <= (py nand px); -- only go low if no disables
    xgame <= xgame_temp;
    ygame <= ygame_temp;
    END behav;
     
    kipman725, Dec 14, 2008
    #1
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  2. kipman725 wrote:
    > The problem is that I get
    > "Warning: Following 20 pins have nothing, GND, or VCC driving datain
    > port" and no logic is produced for this module. It acts like the x
    > and y position counters for the frame can never meet the conditions of
    > the if statments!?!?!


    I expect that x and y are stuck at zero.
    Run a sim and see.

    -- Mike Treseler
     
    Mike Treseler, Dec 14, 2008
    #2
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  3. kipman725

    kipman725 Guest

    On Dec 14, 3:26 pm, Mike Treseler <> wrote:
    > kipman725 wrote:
    > >  The problem is that I get
    > > "Warning: Following 20 pins have nothing, GND, or VCC driving datain
    > > port" and no logic is produced for this module.  It acts like the x
    > > and y position counters for the frame can never meet the conditions of
    > > the if statments!?!?!

    >
    > I expect that x and y are stuck at zero.
    > Run a sim and see.
    >
    >      -- Mike Treseler


    why are x and y stuck at zero though? they are just inputs so should
    be able to take any value within there scope.
     
    kipman725, Dec 14, 2008
    #3
  4. kipman725 wrote:

    > why are x and y stuck at zero though? they are just inputs so should
    > be able to take any value within there scope.


    They are signals, not inputs ports,
    and synthesis works from port to port.
    If no other entity is driving x and y,
    synthesis will see it as all '0'
    and synthesize nothing.

    -- Mike Treseler
     
    Mike Treseler, Dec 14, 2008
    #4
  5. kipman725

    Peter Guest

    > library ieee ;
    > use ieee.std_logic_1164.all;
    > USE ieee.std_logic_arith.ALL;
    > USE ieee.std_logic_signed.ALL;
    > USE ieee.std_logic_unsigned.ALL;
    > use work.all;
    >
    > begin
    > process(clk, x, y)
    >         begin
    >         if (clk='1' and clk'event) then -- rising edge triggered


    As far as I know, you cant use both ieee.std_logic_signed and unsigned
    in the same entity.
    Its better to skip both and use ieee.numeric_std with some changes in
    the code.
    I also noticed that you have x and y in the sensitivity list which is
    incorrect. Only clk shall be in the sensitivity list because its a
    synchronous process triggered only by clk.

    /Peter
     
    Peter, Dec 15, 2008
    #5
  6. kipman725

    Shannon Guest

    Look closely at your logic:

    if (x>71 and x<712) then -- y counter and range check
    xgame_temp <= (xgame_temp + 1);
    px <= '1'; -- x play area indicator
    else
    px <= '0';
    xgame_temp <= "0000000000"; -- reset
    end if;

    The first time through this test let's say x=0. First you check to
    see if x is between two numbers. Ok, no it's not between 71 and 712
    so let's look at the else condition.
    xgame_temp get's set to zero. later on in your code x gets the value
    of xgame_temp. Uh oh! Now x is set to zero again!
    The second time through the loop will be exactly like the first. X
    will never be incremented past zero. Quartus can see this and decides
    well gee I'll just set it to zero for you and delete all this other
    code that won't ever do anything.

    Can you see what you need to do to fix this?

    Shannon
     
    Shannon, Dec 15, 2008
    #6
  7. kipman725

    kipman725 Guest

    I have got it working, the problem was the usage of unsigned and
    signed so by switching to just using signed all was fixed. The logic
    of the if statments is fine and I don't assign anything to x and y. I
    succesfully used this as part of some VHDL that generates a 640*480
    VGA frame with a border.

    --Game Position Counters
    --640*480 Pix play feild
    library ieee ;
    use ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.ALL;
    USE ieee.std_logic_unsigned.all;
    use work.all;

    entity gpc is
    port( clk: in std_logic;
    x : in std_logic_vector (9 DOWNTO 0); -- Frame x position
    y : in std_logic_vector (8 DOWNTO 0); -- Frame y position
    xgame : out std_logic_vector (9 DOWNTO 0); --Game x position
    ygame : out std_logic_vector (8 DOWNTO 0); --Game y position
    disable: out std_logic --Turns off r,g,b when not in play feild
    );
    END gpc;

    ARCHITECTURE behav of gpc is
    SIGNAL xgame_temp : std_logic_vector (9 DOWNTO 0);
    SIGNAL ygame_temp : std_logic_vector (8 DOWNTO 0);
    SIGNAL px, py : std_logic;
    begin
    process(clk)
    begin
    if (clk='1' and clk'event) then -- rising edge triggered
    if (x>71 and x<712) then -- x counter range check
    xgame_temp <= (xgame_temp + 1);
    px <= '1'; -- x play area indicator
    else
    px <= '0';
    xgame_temp <= "0000000000"; -- reset
    end if;
    if (y>16 and y<497) then -- y counter range check
    if (x = 713) then -- Only inc y play at end of line scan
    ygame_temp <= (ygame_temp + 1);
    end if;
    py <= '1';
    else
    py <= '0';
    ygame_temp <= "000000000"; -- reset
    end if;
    end if;
    end process;
    disable <= (py nand px); -- only go low if no disables
    xgame <= xgame_temp;
    ygame <= ygame_temp;
    END behav;
     
    kipman725, Dec 15, 2008
    #7
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