Query on fractional divider logic

[sundar]

Hi All,


I need your help in understanding this fractional divider logic that
is implemented in the following code.





--******************************************************

ClkDiv2 : process(nMr, Clk78) -- divide by 38.88

variable Cnt : integer range 0 to 63;

variable SubCnt : integer range 0 to 32;

begin

if (nMr='0') then

Clk2 <= '0';

Cnt := 0;

SubCnt := 0;

elsif rising_edge(Clk78) then

if (Cnt>18) then

Clk2 <= '1';

else

Clk2 <= '0';

end if;

if (Cnt>37) or ((Cnt>36) and ((SubCnt=0) or (SubCnt=8) or
(SubCnt=17))) then

Cnt := 0;

if (SubCnt>23) then

SubCnt := 0;

else

SubCnt := SubCnt+1;

end if;

else

Cnt := Cnt+1;

end if;

end if;

end process;



--***************************************************


can you explain how the clock division factors for "divide by 38.88"
are achieved?

can you provide any algorithm/formulae for reference?

Regards,
Sundar

 

[Allan Herriman]

Hi All,


I need your help in understanding this fractional divider logic that
is implemented in the following code.





--******************************************************
ClkDiv2 : process(nMr, Clk78) -- divide by 38.88
variable Cnt : integer range 0 to 63;
variable SubCnt : integer range 0 to 32;
begin
if (nMr='0') then
Clk2 <= '0';
Cnt := 0;
SubCnt := 0;
elsif rising_edge(Clk78) then
if (Cnt>18) then
Clk2 <= '1';
else
Clk2 <= '0';
end if;
if (Cnt>37) or ((Cnt>36) and ((SubCnt=0) or (SubCnt=8) or
(SubCnt=17))) then
Cnt := 0;
if (SubCnt>23) then
SubCnt := 0;
else
SubCnt := SubCnt+1;
end if;
else
Cnt := Cnt+1;
end if;
end if;
end process;
--***************************************************


can you explain how the clock division factors for "divide by 38.88"
are achieved?

can you provide any algorithm/formulae for reference?

A fractional-N divider implemented in this way is almost like a regular
counter, except that the terminal count is varied dynamically.

You can see two counters in the design: Cnt and SubCnt.
(Actually that sounds a bit like what I call my co-workers when they have
earned my displeasure.)

The terminal count of Cnt is controlled to be either 38 or 37, depending on
the value of SubCnt. The average value will be 37.88, and given that the
counter starts at 0, the period of the output signal Clk2 will have an
average value of 38.88 input clocks.

SubCnt counts 0 to 24. When it is 0, 8 or 17, the main counter, Cnt,
divides by 38. When SubCnt is any other value, Cnt divides by 39. The
three divide by 38 cycles are spread out like that to minimise jitter.

The output waveform has 25 rising edges for every 972 input clocks, so the
average division is 38.88.
(972 = 3 x 38 + 22 x 39,
and 25 = 3 + 22,
and 972 / 25 = 38.88)

With a 78.88MHz input clock (from your SONET framer or mapper) you will get
exactly 2.000MHz out. There is some jitter on the output, and this will
have an amplitude of about 12ns p-p.


BTW, the Cnt counter in this design is also known as a Dual-Modulus
Prescaler, because it is a frequency divider (a Prescaler) and it has two
different, selectable counts (38 or 39).

Also, this line:

variable SubCnt : integer range 0 to 32;

could be changed to

variable SubCnt : integer range 0 to 31;

as SubCnt never gets above 24.

Regards,
Allan

 

[sundar]

(e-mail address removed):








A fractional-N divider implemented in this way is almost like a regular
counter, except that the terminal count is varied dynamically.

You can see two counters in the design: Cnt and SubCnt.
(Actually that sounds a bit like what I call my co-workers when they have
earned my displeasure.)

The terminal count of Cnt is controlled to be either 38 or 37, depending on
the value of SubCnt. The average value will be 37.88, and given that the
counter starts at 0, the period of the output signal Clk2 will have an
average value of 38.88 input clocks.

SubCnt counts 0 to 24. When it is 0, 8 or 17, the main counter, Cnt,
divides by 38. When SubCnt is any other value, Cnt divides by 39. The
three divide by 38 cycles are spread out like that to minimise jitter.

The output waveform has 25 rising edges for every 972 input clocks, so the
average division is 38.88.
(972 = 3 x 38 + 22 x 39,
and 25 = 3 + 22,
and 972 / 25 = 38.88)

With a 78.88MHz input clock (from your SONET framer or mapper) you will get
exactly 2.000MHz out. There is some jitter on the output, and this will
have an amplitude of about 12ns p-p.

BTW, the Cnt counter in this design is also known as a Dual-Modulus
Prescaler, because it is a frequency divider (a Prescaler) and it has two
different, selectable counts (38 or 39).

Also, this line:


could be changed to


as SubCnt never gets above 24.

Regards,
Allan

Hello Allan,
Thanks for your detailed response.
The explanation of 972 = 3 x 38 + 22 x 39,
and 25 = 3 + 22,
and 972 / 25 = 38.88 has cleared my doubts
Thanks again,
sundar