Ques on HDL: Please help

Discussion in 'VHDL' started by Ignoramus, Jan 28, 2006.

  1. Ignoramus

    Ignoramus Guest

    1. Verilog Variables are:
    A) static
    B) dynamic
    C) auto
    D) not applicable

    2. When level-sensitive and edge-sensitive cases specify different
    output values in an UDP:
    A) the output is unknown
    B) the output is that of level-sensitive
    C) the output is that of edge-sensitive
    D) depending on the behavior of the gate

    3. “reg [7:0] memory [15:0] declares:
    A) 8 words of 16-bits each
    B) 16 words of 8-bits each
    C) not valid Verilog syntax
    D) read only memory

    4. Which of the following is NOT true:
    A) wire and tri nets are used to connect logic elements
    B) logical conflicts from multiple drivers result in unknown for wire nets
    C) multiple drivers are not allowed on wire nets, but allowed on tri nets
    D) wire and tri have the same syntax and semantics

    5. When three delays are specified for Verilog primitives, which one
    determines transition to “x”: (for those primitive gates that allow
    three delays)
    A) the largest
    B) the smallest
    C) the third
    D) depending on the behavior of the gate

    6. Which of the following is NOT true:
    A) register class consists of reg, integer, time and real.
    B) register nets receive new values only through the assignments made
    within procedural blocks
    C) register nets can be driven by primitive gates
    D) registers are used extensively in design at behavior level and the
    application of stimulus.

    7. Which of the following statements is false:
    A) all verilog keywords are lowercase by definition
    B) Only an escaped identifier can contain a white space in it.
    C) Verilog is a free-format lanugage.
    D) Identifiers that do not match in case are considered distinct.

    8. Which of the following statement is false:
    A) At most one input transition may be specified in any table entry
    B) There can be only one initial statement in an UDP
    C) All UDP ports must be declared as scalar inputs or outputs
    D) UDP ports can be inout, but must be defined.

    9. Which of the following type of assignment can be used if the order
    of the assignments to a set of register variables does not matter:
    A) Continuous assignment
    B) Non-blocking procedural assignment
    C) Blocking procedural assignment
    D) Both A and B are correct.

    10. Which of the following statement is not true:
    A) A function can be an operand within an expression.
    B) A function definition implicitly declares a register.
    C) Delay control is allowed in a function, but not event control.
    D) A function cannot enable tasks.
    Ignoramus, Jan 28, 2006
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  2. jens

    jens Guest

    When in doubt, guess "C".
    jens, Jan 29, 2006
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