Hi,
Hans guessed correctly. It was a combined Questa/Catapult/Precision
presentation.
Shame on the presenter, if you couldn't even answer basic questions
yourself after the presentation.
What I could able to understand was -
- As Hans said, Questa is Modelsim-SE + Assertions + Functional
Coverage + Testbench automation + SystemC + "SystemVerilog".
- Questa supports static verification which was not supported till
Modelsim 6.2(support dynamic verification).
- Questa come up with a new verification methodology.
Questa seems to me as a big nice tool for someone who could affort the
cost overhead, but it wont change market as long as it is siginificant
more expensive than a SE license.
The functionality is nice-to-have but not crucial for all designs I
expect to work on in the next month or years.
A good question for testbench automatisation is the question of the
time and effort needed to write a set of good and sufficient
assertions in order to enable the testbench automatisation.
I expect, that you could develop a lot of testbenches yourself in
that time.
And finally, the presentor asked seriously to look for some other
preofession if we are not thinking of updating ourselves with
SystemVerilog.
This might be correct for pure Verilog-Companies. In VHDL-World, you
could expect benefit from SV only when using it as verification
language.
As long as SV for verification needs Questa licenses, only large
companies will or could afford to change from VHDL to SV. A major
commercial factor beside the license fee is the effort to change
existing inhouse resources (tools, rtl-code, verification code,
verification methodology) to SV.
I know only one company [1] in the German spoken area that switched
for all designs from VHDL to SV and this only for testing, the RTL
wont change to SV. I expect to see only few companies in europe
changing from VHDL to SV until 2010.
bye Thomas
[1] in fact only part of a big group
