Question about conditional generate

Discussion in 'VHDL' started by cathy, Nov 27, 2006.

  1. cathy

    cathy Guest

    Hello, All.

    I have a question about the conditional generate statement.
    For my code:

    constant C_BankNumBits : Natural :=1;
    constant C_BankNum :Natural := 2**(C_BankNumBits);

    G_RegBank1 : if(C_BankNumBits=0) generate
    G_RegBank : for i in 0 to (C_BankNum-1) generate
    RegBank : brb8
    port map (
    clka => clk, dina => dina(i), addra => addra,
    wea => wea, douta => douta(i),
    clkb => clk, dinb => dinb(i), addrb => addrb,
    web => web, doutb => doutb(i));
    end generate G_RegBank;
    end generate G_RegBank1;

    ....... other generate statement......
    (here, I want to use different memory size if different bank number is
    used)

    I defined addra as std_logic_vector(11-C_BankNumBits downto 0).
    Addra in the component brb8 is (11 downto 0).
    In this case, I think the above generate statement won't work because
    it doesn't satisfy the conidtion: if(C_BankNumBits=0). But the ISE give
    me the following error when I check the syntax:
    "Width mismatch. Expected width 12, Actual width is 11 for dimension 1
    of addra."

    Can anybody explains this to me?

    Thanks a lot,
    Cathy
    cathy, Nov 27, 2006
    #1
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  2. cathy

    Andy Guest

    You assume that c_banknumbits is 0 in the first assumption, yet it is
    defined as 1.

    Even though the generate statement is not elaborated, the width
    checking is done at analysis (compile) time, which means that it must
    be valid even if the generate statement turns out not to be elaborated.

    Andy


    cathy wrote:
    > Hello, All.
    >
    > I have a question about the conditional generate statement.
    > For my code:
    >
    > constant C_BankNumBits : Natural :=1;
    > constant C_BankNum :Natural := 2**(C_BankNumBits);
    >
    > G_RegBank1 : if(C_BankNumBits=0) generate
    > G_RegBank : for i in 0 to (C_BankNum-1) generate
    > RegBank : brb8
    > port map (
    > clka => clk, dina => dina(i), addra => addra,
    > wea => wea, douta => douta(i),
    > clkb => clk, dinb => dinb(i), addrb => addrb,
    > web => web, doutb => doutb(i));
    > end generate G_RegBank;
    > end generate G_RegBank1;
    >
    > ...... other generate statement......
    > (here, I want to use different memory size if different bank number is
    > used)
    >
    > I defined addra as std_logic_vector(11-C_BankNumBits downto 0).
    > Addra in the component brb8 is (11 downto 0).
    > In this case, I think the above generate statement won't work because
    > it doesn't satisfy the conidtion: if(C_BankNumBits=0). But the ISE give
    > me the following error when I check the syntax:
    > "Width mismatch. Expected width 12, Actual width is 11 for dimension 1
    > of addra."
    >
    > Can anybody explains this to me?
    >
    > Thanks a lot,
    > Cathy
    Andy, Nov 27, 2006
    #2
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  3. cathy

    cathy Guest

    Thank you very much for your help,
    Cathy
    cathy, Nov 28, 2006
    #3
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