Question - aggregates..

Discussion in 'VHDL' started by Kot, Sep 12, 2003.

  1. Kot

    Kot Guest

    -- incr8.vhd

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

    entity incr8 is
    port (
    a : in std_logic_vector(7 downto 0);
    cin : in std_logic;
    dout : out std_logic_vector(7 downto 0);
    cout : out std_logic
    );
    end entity incr8;

    architecture a1 of incr8 is
    signal sum : std_logic_vector(8 downto 0);
    begin
    -- sum <= ('0' & a) + ( 8 downto 1 => '0', 0 => cin ) ;
    -- above line does not work. why?
    sum <= ( '0' & a ) + ( "00000000" & cin ) ;
    cout <= sum(8);
    dout <= sum(7 downto 0);
    end architecture a1;

    -- tool used is Synplicity's Synplify
    Kot, Sep 12, 2003
    #1
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  2. Kot

    Kot Guest

    Hi Tim,
    I tried these two ways but they both don't work:

    sum <= ('0' & a) + ( 0 => cin, others => '0' ) ;
    Error : aggregate with others must be in a constrained context

    sum <= ('0' & a) + ( ( 0 => cin ), ( others => '0' ) ) ;
    Error : Can't convert expression to type std_logic
    Error : Can't convert expression to type std_logic
    (2 identical errors on the same line)

    On the other hand, I get no error for following code (original
    code that had problem) but the result is simply not what I expected :
    sum <= ('0' & a) + ( 8 downto 1 => '0', 0 => cin ) ;

    I can go around the problem but I believed it should work this way
    either. If there's something wrong with the code, I'd like know
    what exactly is wrong to understand better VHDL standard.

    Jihwan Song
    Kot, Sep 15, 2003
    #2
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  3. sum <= ('0' & a) + ( 0 => cin, others => '0' ) ;
    is not correct since what are the others? Remember that it is not required
    for the addition operator that the left and the right operand has the same
    length!

    Here are some solution that will work (I hope)

    sum <= ('0' & a) + ( '0' & cin ) ;
    Notice that in this example both operands do indeed not have the same
    length.
    Operand a, the longest vector, is extended with a zero. This results in an
    output with carry.
    The cin is only concatenated with '0'. The function "+" will automatically
    extend the shortest
    vector to the required length!! (You don't have to make that explicit).

    But you tried that: sum <= ('0' & a) + ( 8 downto 1 => '0', 0 => cin ) ;
    Although it is correct VHDL and will also synthesize ( correctly :) ) the
    result was surprising to you.
    Remember that is a vector is declared that has NO explicit range the vector
    has a "to-direction".
    This means that ( 8 downto 1 => '0', 0 => cin ) will result in a vector "0
    to 8" with the pattern
    cin&"00000000". So the cin is on the left (and not on the right).

    Try: sum <= ('0' & a) + ( 0 to 7 => '0', 8 => cin ) ;
    This will work.

    Another way to solve if you like to write down the length of the vector
    explict is:
    sum <= ('0' & a) + ((a'range=>'0') & cin) ;

    Notice that a is vector (7 downto 0). So ((a'range=>'0') will result is
    00000000, and on the right it is concatenated with cin.

    But I prefer the first short solution :
    sum <= ('0' & a) + ( '0' & cin ) ;

    Egbert Molenkamp


    "Kot" <> schreef in bericht
    news:...
    > Hi Tim,
    > I tried these two ways but they both don't work:
    >
    > sum <= ('0' & a) + ( 0 => cin, others => '0' ) ;
    > Error : aggregate with others must be in a constrained context
    >
    > sum <= ('0' & a) + ( ( 0 => cin ), ( others => '0' ) ) ;
    > Error : Can't convert expression to type std_logic
    > Error : Can't convert expression to type std_logic
    > (2 identical errors on the same line)
    >
    > On the other hand, I get no error for following code (original
    > code that had problem) but the result is simply not what I expected :
    > sum <= ('0' & a) + ( 8 downto 1 => '0', 0 => cin ) ;
    >
    > I can go around the problem but I believed it should work this way
    > either. If there's something wrong with the code, I'd like know
    > what exactly is wrong to understand better VHDL standard.
    >
    > Jihwan Song
    Egbert Molenkamp, Sep 15, 2003
    #3
  4. Kot

    FE Guest

    > sum <= ('0' & a) + ( '0' & cin ) ;
    Great solution Egbert but you could just write:
    sum <= ('0' & a) + cin;
    because in ieee.std_logic_unsigned (the library used by Kot) the operation
    std_logic_vector + std_logic is defined.

    Kot,
    ieee.std_logic_unsigned is not an ieee library (it's a synopsys library) and
    you should use ieee.numeric_std.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    architecture a1 of incr8 is
    signal sum : unsigned(8 downto 0);
    begin
    sum <= unsigned('0' & a) + ('0' & cin); -- with Egbert's solution ( '0' &
    cin)
    cout <= sum(8);
    dout <= std_logic_vector(sum(7 downto 0));
    end architecture a1;

    regards
    fe
    FE, Sep 15, 2003
    #4
  5. Kot

    Kot Guest

    Thank you very much Egbert, fe!
    Both of your answeres were very helpful.

    Jihwan Song
    Kot, Sep 16, 2003
    #5
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