question for to_stdlogicvector( )

[to_verilog]

I'm a guy from Verilog and try to interpret the VHDL codes from other
VHDL guy who left the position. This is the problem I encounter:

LIGBRARY IEEE,STD;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
.......
TYPE bufsize IS range 0 to 96;
SIGNAL temp : STD_LOGIC_VECTOR(0 TO 5);
............

ARCHITECTURE ..........
BEGIN
.........
PROCESS(,)
VARIABLE io : bufsize;
BEGIN
.......
temp <= to_stdlogicvector(natural(io/8),6);
.......
END PROCESS;
END;

When using ModelSim SE 5.5e to compile, the error message seem to tell
me that I'm not allowed to use to_stdlogicvector() in this way. Am I
using the wrong library or anything else? thanks for you help.

 

[VhdlCohen]

The following works:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;


entity e is
end entity e;

architecture y of e is
subtype bufsize is natural range 0 to 96;
signal temp : std_logic_vector(0 to 5);
signal temp2 : unsigned (0 to 5);
begin -- architecture y
process
variable io : bufsize := 50;
begin
temp <= std_logic_vector(TO_UNSIGNED(io, 6));
temp2 <= (TO_UNSIGNED(io/8, 6));
wait;
end process;

end architecture y;

-- vcom -93 t.vhd
-- Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
-- -- Loading package standard
-- -- Loading package std_logic_1164
-- -- Loading package numeric_std
-- -- Compiling entity e
-- -- Compiling architecture y of e
-- %

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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ (e-mail address removed)
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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