question on async D's f/f

Discussion in 'VHDL' started by Amit, Apr 23, 2007.

  1. Amit

    Amit Guest

    Hello group,

    I'm writing my 2nd project in VHDL and trying to change a synch FSM
    (sequence recognizer) to asynch.

    I'm gettnig error on the line which is specificed with Err_1

    1) this statement doesn't conisdered as error by compiler for the
    synch process but is assumed as error for async. Why?

    2) Is my logic correct in terms of Async D's F/F (in asynch:
    process(....) ) ?

    Regards,
    amit



    library IEEE;
    use IEEE.STD_LOGIC_1164.all;

    -- set = Preset
    -- clear = reset

    entity recog0101 is
    port(x, clock, reset, set: in std_logic;
    z : out std_logic);
    end;

    architecture behavior of recog0101 is
    type state_type is (init, saw0, saw01, saw010);
    signal current_state, next_state : state_type;
    begin

    asynch: process(clock, reset, set)
    begin

    if reset = '0' then
    current_state <= current_state; <<<<<<<<<< Err_1
    --elseif rising_edge(clock) then
    -- if set = '0' then
    -- current_state <= next_state;
    -- end if;
    end if;

    end process;

    synch: process(clock)
    begin
    if clock'event and clock = '1' then
    current_state <= next_state;
    end if;
    end process;

    combin: process (current_state, x)
    begin
    z <= '0';
    case current_state is
    when init =>
    if x = '0' then
    next_state <= saw0;
    -- else stay in this state
    end if;
    when saw0 =>
    if x = '0' then
    -- else stay in this state
    else
    next_state <= saw01;
    end if;
    when saw01 =>
    if x = '0' then
    next_state <= saw010;
    else
    next_state <= init;
    end if;
    when saw010 =>
    if x = '0' then
    next_state <= saw0;
    else
    next_state <= saw01;
    z <= '1';
    end if;
    end case;
    end process;
    end behavior;
    Amit, Apr 23, 2007
    #1
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  2. Amit

    Amit Guest

    Re: question on async D's f/f

    On Apr 23, 1:03 pm, Amit <> wrote:
    > Hello group,
    >
    > I'm writing my 2nd project in VHDL and trying to change a synch FSM
    > (sequence recognizer) to asynch.
    >
    > I'm gettnig error on the line which is specificed with Err_1
    >
    > 1) this statement doesn't conisdered as error by compiler for the
    > synch process but is assumed as error for async. Why?
    >
    > 2) Is my logic correct in terms of Async D's F/F (in asynch:
    > process(....) ) ?
    >
    > Regards,
    > amit
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    >
    > -- set = Preset
    > -- clear = reset
    >
    > entity recog0101 is
    > port(x, clock, reset, set: in std_logic;
    > z : out std_logic);
    > end;
    >
    > architecture behavior of recog0101 is
    > type state_type is (init, saw0, saw01, saw010);
    > signal current_state, next_state : state_type;
    > begin
    >
    > asynch: process(clock, reset, set)
    > begin
    >
    > if reset = '0' then
    > current_state <= current_state; <<<<<<<<<< Err_1
    > --elseif rising_edge(clock) then
    > -- if set = '0' then
    > -- current_state <= next_state;
    > -- end if;
    > end if;
    >
    > end process;
    >
    > synch: process(clock)
    > begin
    > if clock'event and clock = '1' then
    > current_state <= next_state;
    > end if;
    > end process;
    >
    > combin: process (current_state, x)
    > begin
    > z <= '0';
    > case current_state is
    > when init =>
    > if x = '0' then
    > next_state <= saw0;
    > -- else stay in this state
    > end if;
    > when saw0 =>
    > if x = '0' then
    > -- else stay in this state
    > else
    > next_state <= saw01;
    > end if;
    > when saw01 =>
    > if x = '0' then
    > next_state <= saw010;
    > else
    > next_state <= init;
    > end if;
    > when saw010 =>
    > if x = '0' then
    > next_state <= saw0;
    > else
    > next_state <= saw01;
    > z <= '1';
    > end if;
    > end case;
    > end process;
    > end behavior;



    I found the problem. please ignore this question.
    Amit, Apr 23, 2007
    #2
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