Question on Comparing two std logic vecter

Discussion in 'VHDL' started by Tha, Apr 10, 2011.

  1. Tha

    Tha

    Joined:
    Apr 10, 2011
    Messages:
    3
    Hi, I am new on VHDL, and I am writing a code that comparing two 32 bits std_logic_vector. If they are equal, a result of all one bits is produce, otherwise, a result of all zero bits is produce.
    However, when I simulate my code, the following warnings appears:
    WARNING: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
    and I didn't get the correct result. My tb values are:
    a = 00000000000001111111111111111111
    b = 00000000000001111111111111111111
    the result should be 32 1's
    but it gave me 32 0's.
    Can anyone please help me out? Thank you so much!

    The following is my code:
    entity ceq is
    port(ra : in std_logic_vector(31 downto 0);
    rb : in std_logic_vector(31 downto 0);
    rt : out std_logic_vector(31 downto 0));
    end ceq;

    architecture ceq_stru of ceq is
    signal rts : std_logic_vector(31 downto 0);
    begin
    comp: process (ra, rb)
    variable count : std_logic_vector (31 downto 0)
    := "00000000000000000000000000000000";
    begin
    rts <= ra xor rb;
    if rts = count then
    rt <= (others => '1');
    else
    rt <= count;
    end if;

    end process comp;

    end ceq_stru;
     
    Tha, Apr 10, 2011
    #1
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  2. Tha

    Tha

    Joined:
    Apr 10, 2011
    Messages:
    3
    Okay, just after I post this thread , I found out why my code doesn't work.

    "Note that this library doesn't allow you to do comparisons on std_logic_vector values. That's because it's impossible for it to determine whether a particular std_logic_vector is representing a signed or unsigned value. To do this, you need to use either the std_logic_unsigned or std_logic_signed libraries."

    referred from http://www.cs.sfu.ca/~ggbaker/reference/std_logic/arith/comp.html
     
    Tha, Apr 10, 2011
    #2
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  3. Tha

    joris

    Joined:
    Jan 29, 2009
    Messages:
    152
    The problem is signal semantics - signals are updated only after "one delta" - that is, at the end of the process.

    It should work correctly after making rts a variable.
     
    joris, Apr 11, 2011
    #3
  4. Tha

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    XOR

    You should be using XNOR. XOR is 0 when the bits are alike, while XNOR is 1.
     
    eliascm, Apr 11, 2011
    #4
  5. Tha

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    XOR Correction

    Sorry, I goofed, you are looking for zeros.
     
    eliascm, Apr 11, 2011
    #5
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