question on timing in synthesizable vhdl

[Mike Treseler]

My question is for a process sensitive to a CLK signal, if the process is
very long and also call a whole list of complex procedures, will this limit
the maximum clock rate of CLK, and will this pose a efficiency problem in
actual hardware,

The length of a process is a matter of style.
Length alone has nothing to do
with efficiency or fmax. The same synchronous design
entity can be described in one process or in
many processes and infer the same hardware.
Long processes may describe both single level
and pipelined structures.

Long processes allows effective use of variables
as registers and makes synthesis do more work for you.
An architecture full of short processes
looks more like schematic netlist using
signals as wires.

-- Mike Treseler

 

[Mike Treseler]

Does this means that the compiler or synthesis tool
may optimize the inferred hardware to pipelined structures even though I use
only 1 long process?.

No. The job of synthesis is to generate
a netlist of device primitives that simulates
the same as the source code. Period.
If you want a pipeline, it must be described
in your source. You many describe the pipeline
with multiple statements in a single process
or with one process per register. It's
up to the designer which is easier to write and read.

-- Mike Treseler

 

[Andy Peters]

Is it true that whether the synchronous long process ends up as a single or
pipeline structure is dependent on how the source is written?

Of course -- if you describe a pipeline, your hardware will be a
pipeline.

However, modern synthesis tools are clever and can optimize the
pipeline. For example, if you write a multiplier and add two registers
after it, the synthesizer will automagically pipeline the multiplier,
potentially allowing for a faster clock rate at the expensive of
pipeline latency.

Also, if it ends up as a single level structure will decrease the maximum
clock rate?

Depends on how much combinatorial logic is required to implement each
path.

-a

 

[Okashii]

Hi people,
I'm new to vhdl so please correct me if I have any conceptual problems. What
I am doing now is trying to convert openmp (a c-like language with
parallelism) to synthesizable vhdl.
My question is for a process sensitive to a CLK signal, if the process is
very long and also call a whole list of complex procedures, will this limit
the maximum clock rate of CLK, and will this pose a efficiency problem in
actual hardware, as I think it will take 1 clock cycle to execute the whole
sequence of statements (giving long propagation delay and hence low clock
rate?). For e.g. if I run 6 processes with the same clock signal, and one of
the process has 3 milliseconds propagation delay, and while the other 5 has
1 nanosecond propagation delay, will the other 5 will also take 3
milliseconds to complete because the longest propagation delay is taken? I
am not very sure whether this will happen, but I just imagine that it will

Thanks in advance!

 

[Okashii]

The length of a process is a matter of style.

Length alone has nothing to do
with efficiency or fmax. The same synchronous design
entity can be described in one process or in
many processes and infer the same hardware.
Long processes may describe both single level
and pipelined structures.

I'm a bit confused here. Does this means that the compiler or synthesis tool
may optimize the inferred hardware to pipelined structures even though I use
only 1 long process?.

 

[Okashii]

No. The job of synthesis is to generate

a netlist of device primitives that simulates
the same as the source code. Period.
If you want a pipeline, it must be described
in your source. You many describe the pipeline
with multiple statements in a single process
or with one process per register. It's
up to the designer which is easier to write and read.

Is it true that whether the synchronous long process ends up as a single or
pipeline structure is dependent on how the source is written?
Also, if it ends up as a single level structure will decrease the maximum
clock rate?

Okashii