question on timing in synthesizable vhdl

Discussion in 'VHDL' started by Mike Treseler, Sep 12, 2005.

  1. Okashii wrote:

    > My question is for a process sensitive to a CLK signal, if the process is
    > very long and also call a whole list of complex procedures, will this limit
    > the maximum clock rate of CLK, and will this pose a efficiency problem in
    > actual hardware,


    The length of a process is a matter of style.
    Length alone has nothing to do
    with efficiency or fmax. The same synchronous design
    entity can be described in one process or in
    many processes and infer the same hardware.
    Long processes may describe both single level
    and pipelined structures.

    Long processes allows effective use of variables
    as registers and makes synthesis do more work for you.
    An architecture full of short processes
    looks more like schematic netlist using
    signals as wires.

    -- Mike Treseler
     
    Mike Treseler, Sep 12, 2005
    #1
    1. Advertising

  2. Okashii wrote:
    >>The length of a process is a matter of style.
    >>Length alone has nothing to do
    >>with efficiency or fmax. The same synchronous design
    >>entity can be described in one process or in
    >>many processes and infer the same hardware.
    >>Long processes may describe both single level
    >>and pipelined structures.

    >
    > Does this means that the compiler or synthesis tool
    > may optimize the inferred hardware to pipelined structures even though I use
    > only 1 long process?.


    No. The job of synthesis is to generate
    a netlist of device primitives that simulates
    the same as the source code. Period.
    If you want a pipeline, it must be described
    in your source. You many describe the pipeline
    with multiple statements in a single process
    or with one process per register. It's
    up to the designer which is easier to write and read.

    -- Mike Treseler
     
    Mike Treseler, Sep 12, 2005
    #2
    1. Advertising

  3. Mike Treseler

    Andy Peters Guest

    Okashii wrote:
    > Mike wrote:
    > > No. The job of synthesis is to generate
    > > a netlist of device primitives that simulates
    > > the same as the source code. Period.
    > > If you want a pipeline, it must be described
    > > in your source. You many describe the pipeline
    > > with multiple statements in a single process
    > > or with one process per register. It's
    > > up to the designer which is easier to write and read.

    >
    > Is it true that whether the synchronous long process ends up as a single or
    > pipeline structure is dependent on how the source is written?


    Of course -- if you describe a pipeline, your hardware will be a
    pipeline.

    However, modern synthesis tools are clever and can optimize the
    pipeline. For example, if you write a multiplier and add two registers
    after it, the synthesizer will automagically pipeline the multiplier,
    potentially allowing for a faster clock rate at the expensive of
    pipeline latency.

    > Also, if it ends up as a single level structure will decrease the maximum
    > clock rate?


    Depends on how much combinatorial logic is required to implement each
    path.

    -a
     
    Andy Peters, Sep 13, 2005
    #3
  4. Mike Treseler

    Okashii Guest

    Hi people,
    I'm new to vhdl so please correct me if I have any conceptual problems. What
    I am doing now is trying to convert openmp (a c-like language with
    parallelism) to synthesizable vhdl.
    My question is for a process sensitive to a CLK signal, if the process is
    very long and also call a whole list of complex procedures, will this limit
    the maximum clock rate of CLK, and will this pose a efficiency problem in
    actual hardware, as I think it will take 1 clock cycle to execute the whole
    sequence of statements (giving long propagation delay and hence low clock
    rate?). For e.g. if I run 6 processes with the same clock signal, and one of
    the process has 3 milliseconds propagation delay, and while the other 5 has
    1 nanosecond propagation delay, will the other 5 will also take 3
    milliseconds to complete because the longest propagation delay is taken? I
    am not very sure whether this will happen, but I just imagine that it will
    :p
    Thanks in advance!
     
    Okashii, Sep 13, 2005
    #4
  5. Mike Treseler

    Okashii Guest

    > The length of a process is a matter of style.
    > Length alone has nothing to do
    > with efficiency or fmax. The same synchronous design
    > entity can be described in one process or in
    > many processes and infer the same hardware.
    > Long processes may describe both single level
    > and pipelined structures.


    I'm a bit confused here. Does this means that the compiler or synthesis tool
    may optimize the inferred hardware to pipelined structures even though I use
    only 1 long process?.
     
    Okashii, Sep 13, 2005
    #5
  6. Mike Treseler

    Okashii Guest

    > No. The job of synthesis is to generate
    > a netlist of device primitives that simulates
    > the same as the source code. Period.
    > If you want a pipeline, it must be described
    > in your source. You many describe the pipeline
    > with multiple statements in a single process
    > or with one process per register. It's
    > up to the designer which is easier to write and read.


    Is it true that whether the synchronous long process ends up as a single or
    pipeline structure is dependent on how the source is written?
    Also, if it ends up as a single level structure will decrease the maximum
    clock rate?

    Okashii
     
    Okashii, Sep 13, 2005
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. walala
    Replies:
    4
    Views:
    1,232
    Technology Consultant
    Sep 9, 2003
  2. aravind

    Synthesizable VHDL

    aravind, Oct 30, 2006, in forum: VHDL
    Replies:
    2
    Views:
    1,305
  3. Ved
    Replies:
    2
    Views:
    1,310
  4. ravi33811

    synthesizable delay using vhdl

    ravi33811, Sep 13, 2007, in forum: VHDL
    Replies:
    0
    Views:
    1,217
    ravi33811
    Sep 13, 2007
  5. ramtinraji
    Replies:
    0
    Views:
    653
    ramtinraji
    Jan 18, 2008
Loading...

Share This Page